Comments (6)
@enjoy-digital: diagram looks great, thanks for creating it, and looking forward to the PR!
One thought: right now the DMA bus is essentially a point-to-point link between Rocket and LiteSDCard, but would you lay it out slightly differently knowing that we might one day (hopefully soon) add LiteSATA to the design, which will also need to be connected to the DMA bus? Making sure that addition will require minimal (visual) re-arrangement of the existing components might be worth a few seconds' thought :)
Finally, not sure if we want to add IRQs to the diagram or not (probably not, but just thinking out loud).
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@gsomlo: Thanks for the feedback, is it better like this? (rearranged the DMA + added IRQs):
Also, do you want the LiteX-Hub logo on it ? (feel free to say no, I just added it here to show you)
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@enjoy-digital: looks good, thanks! Also, LiteX-Hub logo is fine with me (although, visually, I'd probably place it somewhere underneath /dev/ttyUSBX
on the left (probably aligned with the bottom of the rest of the image) where it wouldn't have to stick out vertically. It's a minor thing, perfectly OK where it is now if "bottom-right" is sort-of a standard for logo placement...
from linux-on-litex-rocket.
PR #3 created with:
I'll also share with you the source of this diagram.
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Thanks again, looks really good. Depending on what the source looks like, we might want to make that part of the repo itself -- what do you think?
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resolved by merging PR #3 -- Thanks again @enjoy-digital for putting it together!
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Related Issues (20)
- What needs to be done to get Fedora/Debian working on Rocket? HOT 21
- Booting into linux on simulation HOT 10
- Adjust json2dts.py to work with Rocket HOT 2
- Uploading binary fails at BAUD rates over 230400 HOT 10
- sqrl_acorn (cle-215+) support HOT 2
- is that possible to generate litex rocket with NVDLA? HOT 2
- Boot hang with DE2-115 HOT 6
- toolchains selection issue when building BBL HOT 1
- Debug system instabilities HOT 1
- Simulator UART address HOT 2
- Which cpu architecture to use in BBL building when full rocket (with fp) is used? HOT 2
- Documentation of the varying rocket cpu-variants HOT 2
- Issue with booting HOT 23
- Simulation (using Verilator) failed HOT 1
- Unable to boot Linux - userspace cannot write to console, no busybox shell HOT 7
- litex_sim fails loading opensbi: Liftoff hangs HOT 4
- Unable to boot into linux on simulated SoC - Kernel panic HOT 11
- zifencei + zicsr needed to build BBL HOT 3
- Has anyone tried having this fabricated on the OpenMPW shuttle? HOT 5
- Design doesn't fit on OrangeCrab FPGA HOT 2
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