Comments (2)
from linux-on-litex-rocket.
hi gsomlo, thank you for your reply.
let me clarify my problem.
NVDLA is short for Nvidia Deep Learning Accrelerator. https://github.com/nvdla. Some SoC Designs has included this NVDLA such as Chipyard(Rocket core & NVDLA) https://github.com/ucb-bar/chipyard or ESP(Ariane & NVDLA) https://github.com/sld-columbia/esp. Chipyard is using Chisel3 to generate RTL. I have already checked linux-on-litex-rocket and boot Rocket core on Arty A7 100T successfully, it seems linux-on-litex-rocket will first generate the RTLs(differnet configs) by using rocket-chip(so as Chipyard), then include those RTLs with some top levels. I wonder if I can plugin NVDLA while generate the RTLs? like modify the Chisel configs?
Chipyard and ESP are all using Xilinx IPcores, such as DDR3/4, SGMII, PLL and so on. But I want to implement Rocket core with NVDLA on Cadance Protium prototyping platform, which means I do not use Xilinx workflow and I can't use Xilinx IPcores.
I have 2 ideas,
- First generate RTLs by using Chipyard or ESP, then replace the Xilinx IPcores with Litex open source IPcores.
- Generate rocket core and NVDLA RTL by using linux-on-litex-rocket workflow.
Which one do you think is reasonable?
from linux-on-litex-rocket.
Related Issues (20)
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- Simulator UART address HOT 3
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- Unable to boot into linux on simulated SoC - Kernel panic HOT 11
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- build busybox : fatal error:crypt.h No such file HOT 3
- Repo status HOT 5
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- Booting linux panic on Arty A7-100T 【uart and irq error】 HOT 2
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from linux-on-litex-rocket.