RocketChip standalone build support is deprecated upstream, requires use of SoC frameworks about linux-on-litex-rocket

[gsomlo]

This should be addressed by litex-hub/pythondata-cpu-rocket@85e155f

I'm now going to start a low-key search for a 64-bit rv64gc, fpu, mmu, and s-mode capable RISC-V chip that can boot a real distro (e.g. Fedora) like Rocket chip could. Bonus points if it's written in Verilog, rather than some obscure "write-only" language :P

[mithro]

You probably want to add "maps efficiently to FPGAs" to your requirements.

[mithro]

@gsomlo - BTW BlackParrot might be a good candidate, the UWash team has previously been active with LiteX related stuff and they would probably respond positively to more users. I believe BlackParrot almost goes through Surelog->UDHM->Yosys correctly these days.

[gsomlo]

looks like we're waiting for rocket-chip upstream PRs chipsalliance/rocket-chip#3493 and/or chipsalliance/rocket-chip#3494 to land in master before being able to resume building litex variants with make verilog (but now with the requirement that the $MILL env.var. be set to something "sensible" before running make verilog).

I find that an acceptable compromise.

Though I am still interested in a [system]verilog (or migen) solution, for reasons of "source code understandability" (whatever software engineers call that property :) ) and the somewhat related/resulting "bus factor" -- thanks everyone for all the suggestions!

[gsomlo]

Closing, see litex-hub/pythondata-cpu-rocket#6 (comment) for the current resolution.

We can revisit this if/when upstream rocket (or yosys' ability to handle .sv files) changes.