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I have adopt about different IO standard.

MIPI CSI 2 has 200mv swing voltage at HS mode**(SLVS200)**

but, is it possible to capture these low voltage differential signal with FPGA?

I think that FPGA lvds 2.5V VCCIO IO standard doesn't capture these low voltage differential signal(MIPI)

I reviewed Kicad board design. but I can't find any level shifter IC. Clock lane and data lanes connected
directly LVDS IO pads...

Hi! Sorry, making this a 'new issue' hoping you get a notification of it: this Verilog code package has issues with place and routing on the icebreaker board (ICE40UP5k) through iCECube2, is this because LVDS DDR inputs are hardcoded to map to Bank3 of ice40 devices, and of the icebreaker board there is only banks 0,1,and 2?

thanks, J

Hello, I am studying how to connect a MIPI camera to my xilinx ZYNQ7020 board, and find your repository, it's awesome.
As I only have a ZYNQ development board, which I buy from web seller, it doesn't have MIPI CSI-2 interface, so I am looking for a inter-connect board, just as your FMC board, so that I could buy a OV13850 module from web seller and have a try.
I mostly work as a software engineer so the electrical design is too difficult for me, from the README I read that you have a new FMC board on the road, could you share the material, such as the PCB layout, or where to buy it, so that I can set up the full system? thanks.

Hello
I have two questions.

1. D-PHY spec operates in two modes, HS and low power which use different IO standards such as differential and single ended. How can we support this in an FPGA?
2. Any issue you see in trying to use RocketIO primitives available in virtex-2 pro devices?
   Thanks

David

is ice40 permanently stalled?

I do appreciate you are heavily committed on other open source initiatives!!

have potential interest and/or project, any chance of a headsup?

thanks again