ZCU106 constraint file about fpga-drive-aximm-pcie

[fpgadeveloper]

The constraints in zcu106-hpc0.xdc in the current repo are correct. Your quoted constraints above are not correct - the port0->X0Y11 constraint is necessary to liberate X0Y12 which the tools place by default. We later use another constraint to place port0 at the correct location: X0Y14. We cannot make the placement before X0Y14 is liberated by the constraint port2->X0Y15.

The reason we have to use this convoluted placement method is because Vivado doesn't allow you to assign something to a GT that is already used by something else (if you try, you get an error message, and the project doesn't build). So we need to liberate the GTs before assigning anything to them. We liberate a GT by reassigning whatever it's connected to, to a different GT.