Multiple issues while building the SW project about fpga-drive-aximm-pcie

[fpgadeveloper]

Please pull the latest commit. The SDK is not part of the 2019.2 tools so the SDK script has been reworked for Vitis in the last commits.

[fpgadeveloper]

Also, a software application for the Zynq US+ designs has been added to the latest commit.

[jdlr-at-nrec]

I don't have access to 2019.2. Will it work with 2019.1?

[fpgadeveloper]

In that case you'll have to build the SDK workspace manually (without the script). Create the hardware platform for the ZCU106 using the exported Vivado project, then add a new empty application. Then copy this file into the application sources and it should work:
"C:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\xdmapcie_v1_0\examples\xdmapcie_rc_enumerate_example.c"

[jdlr-at-nrec]

Excellent!

[jdlr-at-nrec]

Followed your recommendation and worked perfectly under 2019.1.

Thank you for your guidance.

[jdlr-at-nrec]

Hello Jeff, Hope you don’t mind but i have become desperate. I had “fpga-drive-aximm-pcie-2018.2_1” running simulation and i don’t even remember how; but i don’t seem to be able to find the test bench i used. You helped get the design to compile and run on our FPGA Drive FMC and that still runs fine and very happy about that. Unfortunately during a purge to make it easier to find my stuff, i deleted the simulation version of the design. I did not spend the time to merge the designs, so i had a executable version and a simulation version. And that was fine. I spent all day trying to rebuild it but still don’t see where else i can look. Today, i cannot remember if you provided me the testbench file or you pointed me to it, or i am just confused. Can you spend a few minutes guiding me to recover it? Thank you Jaime From: Jeff Johnson <[email protected]> Sent: Thursday, April 30, 2020 21:15 To: fpgadeveloper/fpga-drive-aximm-pcie <[email protected]> Cc: Jaime DelosRios <[email protected]>; Author <[email protected]> Subject: Re: [fpgadeveloper/fpga-drive-aximm-pcie] Multiple issues while building the SW project (#7) Closed #7<#7>. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#7 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/APMRQGGX6X3TJXOA64DXDZ3RPIPC5ANCNFSM4MWVSXSA>.

[fpgadeveloper]

Hi Jamie,
I'm sorry but I don't have a testbench for simulating that design, and I've looked through my emails but there's nothing there regarding simulation.
Jeff

[jdlr-at-nrec]

It was completely my confusion. I profusely apologize for wasting your time. Much appreciate your effort, indeed. Jaime From: Jeff Johnson <[email protected]> Sent: Tuesday, June 9, 2020 11:10 To: fpgadeveloper/fpga-drive-aximm-pcie <[email protected]> Cc: Jaime DelosRios <[email protected]>; Author <[email protected]> Subject: Re: [fpgadeveloper/fpga-drive-aximm-pcie] Multiple issues while building the SW project (#7) Hi Jamie, I'm sorry but I don't have a testbench for simulating that design, and I've looked through my emails but there's nothing there regarding simulation. Jeff — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#7 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/APMRQGHIAH3B5FWYXG6J3V3RVZGD5ANCNFSM4MWVSXSA>.