chipsalliance / cores-veer-el2 Goto Github PK

Hi,
I have integrated RISC-V compliance on El2. I have developed a target directory for compliance support. All the changes are made accordingly to branch 1.0.
If you guys are interested, I can send a PR to review.

Thanks,

Above code is used to add DFT override for scan testing on ATE.
If we change this to use two DFT signals instead like below , it will give a lot more flexibility to integrators as we can then independently reset this scan island between patterns without tie-ing it to entire SOC entering/exiting scan_mode.

Current form isn't suitable for DFT arch of large chips.

assign core_rst_l = rst_l & (scan_mode ? scan_reset_ : dbg_core_rst_l);

rvdffppe does not elaborate with it's default WIDTH parameter + no defines.

Proposal: Set WIDTH >=39 since
LEFT = 39 - 31 = 8

This will allow the module to get elaborated independently. Note that this module works fine when included in the larger system since WIDTH is overwritten.

I was running some tests on SweRV and Whisper and compared them I found these logs

log generated by SweRV-EL2

        16 :       #1 0 80000000 595552b7  t0=59555000 ; lui     t0,0x59555000
        22 :       #2 0 80000004 55528293  t0=59555555 ; addi    t0,t0,1365
        28 :       #3 0 80000008 7c029073              ; csrrw   zero,csr_7c0,t0
        33 :       #4 0 8000000c 70041117  sp=f004100c ; auipc   sp,0x70041000
        38 :       #5 0 80000010 ff410113  sp=f0041000 ; addi    sp,sp,-12
        39 :       #6 0 80000014 00002805  ra=80000016 ; c.jal   0x80000044
        48 :       #7 0 80000044 00001141  sp=f0040ff0 ; c.addi  sp,-16
        49 :       #8 0 80000046 0000c622              ; c.swsp  s0,0xc [f0040ffc]
        50 :       #9 0 80000048 00000800  s0=f0041000 ; c.addi4spn s0,0x10
        51 :      #10 0 8000004a 41bd5593  a1=00000000 ; srli    a1,s10,27
        52 :      #11 0 8000004e 00004781  a5=00000000 ; c.li    a5,0
        53 :      #12 0 80000050 0000853e  a0=00000000 ; c.mv    a0,a5
        54 :      #13 0 80000052 00004432  s0=00000000 ; c.lwsp  s0,0xc [f0040ffc]
        55 :      #14 0 80000054 00000141  sp=f0041000 ; c.addi  sp,16
        56 :      #15 0 80000056 00008082              ; c.jr    ra
        58 :      #16 0 80000016 50580297  t0=d0580016 ; auipc   t0,0x50580000
        59 :      #17 0 8000001a fea28293  t0=d0580000 ; addi    t0,t0,-22
        60 :      #18 0 8000001e 0ff00313  t1=000000ff ; addi    t1,zero,255
        61 :      #19 0 80000022 00628023              ; sb      t1,0(t0) [d0580000]
        62 :      #20 0 80000026 00004305  t1=00000001 ; c.li    t1,1 

log generated by Whisper

#1 0 80000000 595552b7 r 05         59555000  lui      x5, 0x59555
#2 0 80000004 55528293 r 05         59555555  addi     x5, x5, 1365
#3 0 80000008 7c029073 c 07c0       59555555  csrrw    x0, mrac, x5
#4 0 8000000c 70041117 r 02         f004100c  auipc    x2, 0x70041
#5 0 80000010 ff410113 r 02         f0041000  addi     x2, x2, -12
#6 0 80000014     2805 r 01         80000016  c.jal    . + 0x30
#7 0 80000044     1141 r 02         f0040ff0  c.addi   x2, -0x10
#8 0 80000046     c622 m f0040ffc   00000000  c.swsp   x8, 0xc
#9 0 80000048     0800 r 08         f0041000  c.addi4spn  x8, 0x4
#10 0 8000004a 41bd5593 r 0b         00000000  srai     x11, x26, 27
#11 0 8000004e     4781 r 0f         00000000  c.li     x15, 0x0
#12 0 80000050     853e r 0a         00000000  c.mv     x10, x15
#13 0 80000052     4432 r 08         00000000  c.lwsp   x8, 0xc
#14 0 80000054     0141 r 02         f0041000  c.addi   x2, 0x10
#15 0 80000056     8082 r 00         00000000  c.jr     x1
#16 0 80000016 50580297 r 05         d0580016  auipc    x5, 0x50580
#17 0 8000001a fea28293 r 05         d0580000  addi     x5, x5, -22
#18 0 8000001e 0ff00313 r 06         000000ff  addi     x6, x0, 255
#19 0 80000022 00628023 m d0580000   000000ff  sb       x6, 0x0(x5)

at instruction #10 there is a mismatch

 51 :      #10 0 8000004a 41bd5593  a1=00000000 ; srli    a1,s10,27 // EL2

#10 0 8000004a 41bd5593 r 0b         00000000  srai     x11, x26, 27 //Whisper

Hi,

While synthesizing SweRV-EL2 by using dc(2016.03), I got some error messages (unknown width).
Those are related to pt parameter, as follows,

  1. $clog2(pt.xxx)
  2. (pt.xxx)'(sig)

And, I can fix the errors by changing the codes, as follows,

  1. localparam xxx=pt.xxx; $clog2(xxx);
  2. localparam xxx=pt.xxx; (pt)'(sig)

Please check what the problem is.

Thanks.

Hi,

I am trying to synthesis swerv-el2 by using design compiler.
I got some syntax error messages while analyzing it.
They seem to be related to 'package' and 'include'.
Actually, because I am not good at synthesis work, I don't know what to do.
Is there a kind of synthesis script template for swerv-el2 ?

Thanks in advance.

re: module rvsyncss, module rvsyncss_fpga

"lib/beh_lib.sv"

1. Why do we have a multibit wide synchronizer with no handshake mechanism? You can't reliably synchronize a multibit bus unless it's grey-coded.

2. A single bit synchronizer must be of configurable depth and/or readily replaceable by integrator specific synchronizers.
   2-bit depth synchronizers may not comply with integrator/foundry design rules or practice.

Recommendation: Add define for synchronizer depth and/or define for ready replacement of the synchronizers by the integrator.

Coremark score from my simulation is lower than official score (3.6).
My simulation results are as follows,
- default + cmark : 2.42
- high_perf + cmark : 2.42
- high_perf + cmark_dccm : 3.42
- high_perf + cmark_iccm : 3.43
Please let me know how to get official coremark score (3.6).
Thank you.

Hi,

I have been experimenting a bit with EL2 now. Got far enough to run Zephyr on a slightly modified SweRVolf SoC in verilator and have produced an FPGA image of SweRVolf with EL2 for the Nexys A7 board. I will soon submit a PR with the FuseSoC support to easily run this, once I have confirmed it works for Verilator, Modelsim and Vivado. And once the core is publicly released I will also add support in SweRVolf to select between EH1 and EL2 (or create a new SweRVolf variant for EL2, whatever turns out to be the easiest solution). This will give us a whole system for EL2 with spi, uart, debug interface, RAM, GPIO.. etc.

Some observations so far:

• The default target produces a system that is too large for the FPGA on the Nexys A7 board. Using the typical_pd config it will fit.

• I have not tested the FPGA image on a board and I don't think there's any point in doing that yet. With a 50MHz clock I'm getting setup violations of 29 ns on some internal paths in the core. I haven't fully investigated this yet, but I see that the worst offenders have paths which are 53 logic levels deep. From a quick look at the timing report it looks like the FFs aren't mapped correctly but I haven't figured out why yet. I suspect it has to do with the clock gating and the parts around mfdht in el2_dec_tlu_ctl seems like a good place to start the investigation. Hopefully we can come up with something that is FPGA-friendly without impacting the ASIC targets. In the meantime I might try to run it with a 25MHz clock to see if it at least can run properly on an FPGA.

• Verilator simulations appear to be quite a bit slower than running the same thing on EH1. The only clue I have is that verilator complains wildly about not being able to optimize certain parts (UNOPTFLAT) but it could be something completely different.

Hello,

I see in the Reference Manual that a 'core load' (e.g. from DCCM) that has a fault will lead to a precise exception (table 2.4). Suppose the load fault is due to a failing ECC check (normally a late arriving signal) and suppose the faulting load is followed by a 'core store' (e.g. to the DCCM). Assuming that this store will be cancelled/suppressed, can you tell me which signal in the RTL takes care of that? Should I therefore also expect this signal to become a timing critical input to the DCCM?

├── el2_pdef.vh # Parameter structure definition

Values defined in el2_pdef.vh are defined as "bit", which is 2-state only variable.
Since standard verification flows wish to model "X" propagation, these variables should be multi-state "logic" instead of "bit".

Example:
bit [7:0] BHT_ADDR_HI;

Required for support for "X" propagation modelling in simulation:
logic [7:0] BHT_ADDR_HI;

So cmark scores are dependent on which version of the compiler you use and which flags.

Give the command below a try. With gcc 9.3 this yielded CM 3.61.

Thanks.

run.int make -f $RV_ROOT/tools/Makefile verilator target=default CONF_PARAMS='-set=btb_size=512 -set=bht_size=2048' TEST=cmark_dccm TEST_CFLAGS='-finline-limit=400 -mbranch-cost=1 -Ofast -fno-code-hoisting -funroll-all-loops'

VerilatorTB: Start of sim

DCCM pre-load from f0040000 to f00416d0
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 277305
Total time (secs): 277
Iterat/Sec/MHz : 3.61
Iterations : 1
Memory location : STATIC
seedcrc : 0xo9p5
[0]crclist : 0xo714
[0]crcmatrix : 0x1pn7
[0]crcstate : 0x8o3k
[0]crcfinal : 0xo714
Correct operation validated. See readme.txt for run and reporting rules.
TEST_PASSED

Originally posted by @robertgolla in #12 (comment)

Dear robertgolla,

I am sorry for the late reply.
Because my issue is not cleared yet, I open this issue again.
Please understand the situation.

I applied new version of gcc (v9.2) and the options that you provided.
However, I got errors with your options, as below.
The error iseems to be related to the option '-finline-limit=400'.
If I remove the option '-finline-limit=400', there is no error.
But the coremark score is 3.46 which is lower than your result.

Please check again if there is any other condition that I missed.
Thank you very much.

[with '-finline-limit=400']

riscv64-unknown-elf-gcc -Isnapshots/default -finline-limit=400 -mbranch-cost=1 -Ofast -funroll-all-loops -mabi=ilp32 -march=rv32imc -nostdlib -c /home/kdlee/work/riscv/chipsalliance/swerv_el2/Cores-SweRV-EL2/testbench/asm/cmark_dccm.c -o cmark_dccm.o
Building cmark_dccm
riscv64-unknown-elf-ld -m elf32lriscv --discard-none -T/home/kdlee/work/riscv/chipsalliance/swerv_el2/Cores-SweRV-EL2/testbench/asm/cmark_dccm.ld -o cmark_dccm.exe cmark_dccm.o
riscv64-unknown-elf-ld: section .data LMA [0000000000010000,00000000000106ad] overlaps section .text LMA [0000000000000000,00000000000108d9]
/home/kdlee/work/riscv/chipsalliance/swerv_el2/Cores-SweRV-EL2/tools/Makefile:139: recipe for target 'program.hex' failed
make: *** [program.hex] Error 1

[without '-finline-limit=400']

riscv64-unknown-elf-gcc -Isnapshots/default -mbranch-cost=1 -Ofast -fno-code-hoisting -funroll-all-loops -mabi=ilp32 -march=rv32imc -nostdlib -c /home/kdlee/work/riscv/chipsalliance/swerv_el2/Cores-SweRV-EL2/testbench/asm/cmark_dccm.c -o cmark_dccm.o
Building cmark_dccm
riscv64-unknown-elf-ld -m elf32lriscv --discard-none -T/home/kdlee/work/riscv/chipsalliance/swerv_el2/Cores-SweRV-EL2/testbench/asm/cmark_dccm.ld -o cmark_dccm.exe cmark_dccm.o
riscv64-unknown-elf-objcopy -O verilog --only-section ".data*" --change-section-lma .data*-0x10000 cmark_dccm.exe data.hex
riscv64-unknown-elf-objcopy -O verilog --only-section ".text*"  cmark_dccm.exe program.hex
riscv64-unknown-elf-objdump -S  cmark_dccm.exe > cmark_dccm.dis
riscv64-unknown-elf-nm -f posix -C cmark_dccm.exe > cmark_dccm.tbl
Completed building cmark_dccm
./obj_dir/Vtb_top

VerilatorTB: Start of sim

DCCM pre-load from f0040000 to f00485b0
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 289770
Total time (secs): 289
Iterat/Sec/MHz   : 3.46
Iterations       : 1
Compiler version : GCC9.2.0
Compiler flags   : -O2
Memory location  : STATIC
seedcrc          : 0xo9p5
[0]crclist       : 0xo714
[0]crcmatrix     : 0x1pn7
[0]crcstate      : 0x8o3k
[0]crcfinal      : 0xo714
Correct operation validated. See readme.txt for run and reporting rules.
TEST_PASSED

Finished : minstret = 295805, mcycle = 307183
See "exec.log" for execution trace with register updates..

- /home/kdlee/work/riscv/chipsalliance/swerv_el2/Cores-SweRV-EL2/testbench/tb_top.sv:337: Verilog $finish

VerilatorTB: End of sim

I have a question the memory files u have provided used for ICCM, DCCM and icache are they synthesize able or one have to change with available SRAM's.

Greetings!!
I am currently understanding the branch prediction mechanism of SweRV El2 and I am captured by alot of confusions. It would be appreciated if I get to know about the following questions:
1- Overveiw of branch prediction implemented in El2
2- Why we are using hashing and folding for Ghr's and PC
3- Why there are multiple GHR's
4- How many are the algorithms involved in this module and what are those ?
5- Implementation of BHT
6- Any example you can give to explain the whole mechansim in steps
7- LRU

Hello,
I am trying to run the test on both SweRV EL2 and whisper ISS to check the functionality of the core before and after adding some features.
I am facing an issue that the logs files i am getting from both sides are totally different. I am generating the program.hex file from the SweRV EL2 and used it to simulate on both SweRV EL2 and whisper ISS. But the log files shows that the whisper ISS used some predefined instruction which SweRV EL2 don't.
Is there is something which i am missing.
I am attaching the log snaps also for reference.
Whisper ISS Log File

SweRV_EL2 Log file

Program.hex file

I am working on latest repository and running the core through Vivado. On the synthesis step, syntax error is displayed on the terminal. On the further digging into the design , I found that rvjtag contains the systemVerilog constructs i.e. logic and always_comb while the file type is verilog. Am I getting it right or there is different reason for that?

Synchronizers need special handling and are usually hardened cells that include both the flops and have much better MTBF.
Using dedicated cells also helps in keeping the data delay between the two flops to minimum that further helps in improving MTBF.

Its a generally accepted practice for reusable IPs to use a dedicated module for synchronizers that can be replaced by integrators with their custom cells.

VeeR core has such synchronizers at below places, I would suggest replacing them with a module which is defined at a place that integrators can replace with their own implementations.

dmi_jtag_to_core_sync.v and (el2_dbg.sv, line 277) has behavioral code for flops acting as synchronizers.

Hello, I want to use the debug module for debugging the core. Is there any reference manual which I can follow to see how can I debug the SweRV EL2.
Or is it possible to debug the core using gdb commands?

Hello

I am a final year undergraduate student having some experience in SystemVerilog. Currently working on a project which includes integration of SweRV into SoC.
I've configured internal timer interrupt in SweRV-El2 but want to know how exactly I can write an interrupt service routine for that interrupt.
With gratitude,
Rehan Ejaz

I am looking at exploring an ASIC RV32 implementation for area/power studies.
Would you have a document that describes your ASIC synthesis flow?
Since I am looking at academic work here, I have access to the open Yosys tool (for synthesis) and an open source 45nm library.

Thanks for any help or pointers to information.

Best Regards
Nagendra

Hi,
I am trying to build the EL2 design for the Intel Cyclone 10 GX FPGA. This is using the free license within Quartus Prime Pro 21.2.

I am having issues with the el2_param.vh and el2_pdef.vh header files with the following error message:
Error(13406): Verilog HDL error at el2_param.vh(1): object "el2_param_t" is not declared

It looks like when Quartus evaluates el2_param.vh it does not know anything about the typedef in el2_pdef.vh.

I am including the header files in the design using the following command:
set_global_assignment -name SEARCH_PATH "../../../tools/snapshots/default"

I have attached the tcl script files I am using to build the project. They were located in a folder at CORES-SWERV-EL2/syn/cyclone10gx To build the project I run quartus_sh -t test_app.tcl in Linux. The .qpf project file will then be in the work folder below.

From what I understand the SystemVerilog support in Quartus Prime Pro is much better than in the older Lite software versions, so hopefully I am not too far off. Could anyone give me some advise on how to build the SweRV EL2 for this FPGA?

Any help would be much appreciated.

Thanks

David

cyclone10gx.zip

Code has hand-instantiated clock gating cells which are defined in below library.

swerv_el2/rtl/lib/beh_lib.sv
module `TEC_RV_ICG

Generally such clock gates are not synthesized, rather a specific specially design cells is picked up from tech library as we don't want any random unbalanced combo logic on clock path, and timing has to be carefully done.

I do see this particular module being different from the rest in library and using a define for module name. So I am guessing that there was an intent to handle this differently and perhaps allow it to be replaced without having to edit the riscv core code.

But I am not able to see how to achieve that - could someone please clarify?

Hi, @jrahmeh @aprnath @olofk
I would like to know if anybody has run compliance on EL2.
I am currently running compliance (branch 1.0) on EL2 for "I" instructions. I am having an issue that when the tests are running, the behavior of the core interrupted the test as the core hits max cycle count (2000000) and stops.
Iam referencing swervolf compliance for now.I have written the halt logic in compliance_test.h:

		la a0, data_begin;	 \
                la a1, data_end; \
                li a2, 0xf004f000; \   #dccm address
        extract_data: \
        		lw a4, 0(a0); \
        		beq a0, a1, halt; \
        		addi a0, a0, 4; \
        		sw a4, 0(a2); \ #store signatures to dccm address
        		j extract_data; \
        halt: \
        		li a5,0xf00400ff; \ 
                        sw a4,0(a5);            \ #core finish simulation when 0xf00400ff encounters
                        nop;

For writing a signature file, I have written this logic in el2_swerv_wrapper.sv

  reg [1023:0]  signature_file;
   integer 	f = 0;
   initial begin
      if ($value$plusargs("signature=%s", signature_file)) begin
	 $display("Writing signature to %0s", signature_file);
	 f = $fopen(signature_file, "w");
      end
   end

   always @ (posedge clk) begin
        if(dccm_wr_addr_lo == 15'hf000) begin
		    /*if (|f)*/ $fdisplayh(f, dccm_wr_data_hi[31:0]);
            $display("%h",dccm_wr_data_hi[31:0]);

   end
        if(dccm_wr_addr_lo == 15'h00ff && dccm_wr_addr_hi == 15'hf004) begin
            $display("\nTest finished !");
            $finish;
        end
   end

My linker file is

OUTPUT_ARCH( "riscv" )
ENTRY(_start)

SECTIONS
{
  . = 0x0;
  .text.init : { *(.text.init) }
  . = ALIGN(0x1000);
  .tohost : { *(.tohost) }
  . = ALIGN(0x1000);
  .text : { *(.text) }
  . = ALIGN(0x1000);
  /*  . = 0x80000;*/
  .data : { *(.data) }
  .data.string : { *(.data.string)}
  .bss : { *(.bss) }
  _end = .;
}

I have define a hex loading logic in tb_top here :

				if ($value$plusargs("ram_init_file=%s", ram_init_file)) begin
					 $display("Loading RAM contents from %0s", ram_init_file);
					 $readmemh(ram_init_file, imem.mem);
					 $readmemh(ram_init_file, lmem.mem);
                     $display("imem.mem = %h",imem.mem[0][7:0]);
                     $display("imem.mem = %h",imem.mem[1][7:0]);
                     $display("lmem.mem = %h",lmem.mem[0][7:0]);
                     $display("lmem.mem = %h",lmem.mem[1][7:0]);
				end
                else begin
                            $readmemh("program.hex",  lmem.mem);
                            $readmemh("program.hex",  imem.mem);
                end

I have a few questions regarding that

1. I am trying to load hex in the imem. But the format of instructions is word align not byte aligned. Something like this:

0000809300001097
1111011311111137
000001130080006F
000010970020A023
22222137FE808093
0000021722210113
0002006701020213

I think since imem is byte align, the instructions are not getting loaded properly.

I am not sure if I understood the documentation correctly, but it seems like the WFI (wait for interrupt) instruction is not implemented? Or rather just implemented as NOP

These are the only references I could find to wfi:

Docs 5.5.2

Note: WFI is another candidate for a function that stops the core temporarily. Currently, the WFI instruction is
implemented as NOP, which is a fully RISC-V-compliant option. 

This one is in the Core Pause section, and it could mean that the core can be paused with WFI, but it is equivalent to NOP in the EL2 implementation?

And 7.5

37 NOP is an ALU operation. WFI is implemented as a NOP in VeeR EL2 and, hence, counted as an ALU operation was well. 

Any plans to support it, so that the core goes to C3 (sleep) state after the WFI?
If so can you estimate the complexity and give guidelines on implementing it?

Hi,
I was trying to load and store transactions through DCCM. The region address inside the document is 0x0008_0000 (page 17). But, I have noticed no change in transitions of DCCM signals.
Later, I found out that the starting and ending address of DCCM is 0xf0040000 to 0xf004ffff.
Is that a documentation error?

I'm trying to run the dhry test using this command: "make -f $RV_ROOT/tools/Makefile verilator TEST=dhry"

I am met with this error:

/home/csmith/Cores-VeeR-EL2/third_party/picolibc/install/picolibc/riscv64-unknown-elf/include/inttypes.h:313:3: error: unknown type name 'intmax_t'
313 | intmax_t quot;
/home/csmith/Cores-VeeR-EL2/third_party/picolibc/install/picolibc/riscv64-unknown-elf/include/inttypes.h:324:8: error: unknown type name 'uintmax_t'
324 | extern uintmax_t strtoumax(const char *__restrict, char **__restrict, int);
/home/csmith/Cores-VeeR-EL2/third_party/picolibc/install/picolibc/riscv64-unknown-elf/include/stdio.h:81:9: error: unknown type name 'uint16_t'
81 | typedef uint16_t __ungetc_t;
| ^~~~~~~~
/home/csmith/Cores-VeeR-EL2/third_party/picolibc/install/picolibc/riscv64-unknown-elf/include/stdio.h:308:1: error: unknown type name 'ssize_t'; did you mean '_ssize_t'?
308 | ssize_t getdelim(char **__restrict lineptr, size_t *__restrict n, int delim, FILE *__restrict stream);
| ^~~~~~~

I don't understand why it is not working. I was able to get the hello_world function to work but this one is not.

Thanks for any help. :)

Scenario:

1. Core is halted which turns off clk
2. Core wakes up (i_cpu_run_req_d1 is asserted) and tlu_flush_path_r has next PC value
3. Clk is active 1 cycle after cpu_run_req_d1 is asserted
4. tlu_flush_path_r_d1 flop does not sample the next PC value on the first clk edge after core wakes up and remains at 0
5. The 0 value is propagated to mepc, core executes from instr 0 once again and the test goes in an infinite loop

Please use smoke_test_clk_gating to reproduce the issue in Verilator

While i was simulating the SweRV core on verilator. I found that it created few header files in the snapshot/default/ folder. One of the file is pd_define.vh. In that file I have encounter a line which says

`define TEC_RV_ICG HDBLVT16_CKGTPLT_V5_12

Now is the value after TEC_RV_ICG indicates some physical library cell which is used for clock gating. If yes than what does this mean as to which physical library it belongs. Does it belong to 65nm technology or something else and of which vendor?

Thanking you in advance

Code snippet
address : instruction
20003d84: auipc x16, 0xfffc
20003d88: lw x16, 776(x16)

'lw' caused the load region prediction error. Because the value(20003d84+0xfffc000=2ffffd84) of x16 was not in the region of DCCM.

Is there a workaround to avoid the error? Thanks!

I use EL2 v1.4.

Usually, we hide all the assertion code in RTL from frontend tools like synthesis/lint etc.
The core has used below define to add guard against asserts. So we could "not define" this and asserts should get excluded.
However, since this define is already getting set in common_defines.sv directly which has other design defines as well, there is no way to unset this without editing the code.

swerv_el2/rtl/common_defines.sv: `define RV_ASSERT_ON

Should we move this define to outside of design code, so that it is set in verif environment only and not seen by design tools?

Hi all,

I am trying to install the RISC-V GNU toolchain from source in order to test this core.

I followed the guidelines to install the toolchain (2022.03.25 version), opting for the multilib option.

# Clone the repository
git clone https://github.com/riscv/riscv-gnu-toolchain --recursive
cd riscv-gnu-toolchain/

# Checkout 2022.03.25 version
git checkout 2022.03.25

# Configure as multilib and make
./configure --prefix=/opt/riscv --enable-multilib
make

After that, when I execute the following command to see the supported archs:

riscv64-unknown-elf-gcc --print-multi-lib

.;
rv32i/ilp32;@march=rv32i@mabi=ilp32
rv32im/ilp32;@march=rv32im@mabi=ilp32
rv32iac/ilp32;@march=rv32iac@mabi=ilp32
rv32imac/ilp32;@march=rv32imac@mabi=ilp32
rv32imafc/ilp32f;@march=rv32imafc@mabi=ilp32f
rv64imac/lp64;@march=rv64imac@mabi=lp64

Then, I cloned the SweRV-EL2 RISC-V core, and try to run the hello_world simulation, the following error appeared when I build hello_world.o:

Did I forget something in the configuration stage?

Thank you in advance!

Hi,

I synthesized SweRV-EL2 and Rocket Chip with default configuration
Rocket Chip can be synthesized up to 500MHz without timing slack.
However, SweRV-EL2 can be synthesized up to 300MHz without timing slack, in the same condition.
SweRV-EL2 is very slower than Rocket Chip.
Is it reasonable results?
Could you please give me a comment on the result.

Thanks.

is this path is false path?

Greetings,

I have perused this repository and I think it would be a good idea to formally verify the SweRV-EL2 core using riscv-formal (https://github.com/SymbioticEDA/riscv-formal).

RISC-V formal has been applied for formal verification of picorv32 and Vexriscv cores that implement the RV32IMC Instruction set. Since the SweRV EL2 implements RV32IMC, formally verifying it using RISC-V Formal should not be too difficult.

I am a final year undergraduate with some experience in SystemVerilog and computer architecture. I have installed Symbiotic EDA formal verification tools on my system. I am going to work on this project.

Thanks,
Shashank V M

Hello,

I was trying to run tests for typical_pd target, but the program hangs at the beginning.
For example, when I run the test dhry (testbench/tests/dhry) using the following command:

make TEST=dhry target=typical_pd

The output of exec.log is:

//   Cycle : #inst    0    pc    opcode    reg=value   ; mnemonic
        16 :       #1 0 80000000 595552b7  t0=59555000 ; lui t0, 0x59555000
        22 :       #2 0 80000004 55528293  t0=59555555 ; addi t0, t0, 1365
        28 :       #3 0 80000008 7c029073              ; csrrw zero, csr_7c0, t0
        33 :       #4 0 8000000c 70048117  sp=f004800c ; auipc sp, 0x70048000
        38 :       #5 0 80000010 63410113  sp=f0048640 ; addi sp, sp, 1588
        39 :       #6 0 80000014 5ee000ef  ra=80000018 ; jal ra, 0x80000602
        48 :       #7 0 80000602 f0040737  a4=f0040000 ; lui a4, 0xf0040000
        49 :       #8 0 80000606 0000716d  sp=f0048530 ; c.addi16sp -272
        50 :       #9 0 80000608 5b870713  a4=f00405b8 ; addi a4, a4, 1464
        51 :      #10 0 8000060c f00407b7  a5=f0040000 ; lui a5, 0xf0040000
        52 :      #11 0 80000610 5d878793  a5=f00405d8 ; addi a5, a5, 1496
        53 :      #12 0 80000614 00072f03  t5=00000000 ; lw t5, 0(a4) [f00405b8]
        54 :      #13 0 80000618 00472e83  t4=00000000 ; lw t4, 4(a4) [f00405bc]
        55 :      #14 0 8000061c 00872e03  t3=00000000 ; lw t3, 8(a4) [f00405c0]
        56 :      #15 0 80000620 0000d9da              ; c.swsp s6, 0xf0 [f0048620]
        63 :      #16 0 00000000 00000000              ; .short 0
        72 :      #17 0 00000000 00000000              ; .short 0
        76 :      #18 0 00000000 00000000              ; .short 0
        80 :      #19 0 00000000 00000000              ; .short 0
        84 :      #20 0 00000000 00000000              ; .short 0
        88 :      #21 0 00000000 00000000              ; .short 0
        92 :      #22 0 00000000 00000000              ; .short 0
        96 :      #23 0 00000000 00000000              ; .short 0
       100 :      #24 0 00000000 00000000              ; .short 0 

As we can see the program hangs at the beginning. I think it's related with the stack or the linker. Any ideas?
Is there an example with typical_pd that I could follow?
I am using Verilator 4.032 2020-04-04 rev v4.032-5-gbfcd779c

At CoreMark Test ，
I achieved 3.62 ，lower than the official website‘s value of 4.3
How to configure to reach 4.3 in the CoreMark test

RISCV core has assertions guarded by `ifdef RV_ASSERT_ON​

RV_ASSERT_ON is always enabled in src/rtl/riscv_core/rtl/common_defines.sv​

ifndef VERILATOR​ define RV_ASSERT_ON ​
`endif​

Recommendation:​
Add `ifndef VEEREL2_SYNTHESIS or similar in addition to VERILATOR blocker.

Additionally -
Recommend all macro defines have VEEREL2 or similar prefix.

Example: VERILATOR -> VEEREL2_VERILATOR

Note that macro defines are global namespace. We must avoid simple names with reasonable opportunity for collision at integration level.

Hi,
I saw these lines in el2_ifu.sv file
https://github.com/chipsalliance/Cores-SweRV-EL2/blob/7045b803cab825bc3bb3dbca0cb019e55098acc4/design/ifu/el2_ifu.sv#L340-L362
If we see line num 340, it says:
https://github.com/chipsalliance/Cores-SweRV-EL2/blob/7045b803cab825bc3bb3dbca0cb019e55098acc4/design/ifu/el2_ifu.sv#L340-L341
That on every falling edge of clock, if mcyclel value = 32'h00000010 then we will see all the $display statements.
However, when I write the csr mcyclel with 32`h00000010 it does nothing.

Can anybody help me out about how can I generate all the display statements? As I am currently understanding branch prediction of SweRV EL2, visualizing the results with the help of display statement would speedup my progress.

Thankyou,

Hi,

Thanks for the repository.
I got this error in Vivado 2020.1:
[HDL 9-849] Syntax error : file ended before end of clause. ["../Cores-SweRV-EL2/snapshots/default/el2_param.vh":156]
Seems like the parameter instance is not parsed correctly.

Also, what is the highest frequency I can expect on FPGA?

Thanks

As the Swerv have an method to preload the ICCM and DCCM when simulating it on verilator. Will the same task will work on ASIC flow or have to came up with other technology to pre-load the ICCM and DCCM

VeeR defines must be uniquified to avoid collision/redefinition when multiple VeeR cores are instantiated in a single design.

Since verilog macro defines are global namespace, they must be uniquified to avoid macro redifinition collision against other common IP names and multi-VeeR usercases.

The following are generic and subject to contention:

common_defines.vh
define REGWIDTH 32 define CLOCK_PERIOD 100
`define TOP tb_top

el2_param.vh
Most everything.
From a generic perspective, VeeR users should be able to integrate mutliple Veer configurations in parallel without collision.
Hence, anything "defined" in {veer.config -default} must not collide with defines in {veer.config -high_perf}.
Defines must be uniquified allowing multiple concurrent instantiation of differently configured VeeR cores.

Today:
`define FOO 0x1

Recommended
VeeR default config: `define VEER_default_FOO 0x1
Veer high_perf config: `define VEER_high_perf_FOO 0x2

Hello i want to know does the feature of Machine timer interrupt is enable in the new branch of SweRV El2. As previously i got a response that
timer_int input is not configurable and causes another interrupt than PIC interrupts. FIR feature is not activated with timer interrupt.

Hello i am trying to configure the PIC to handle the external interrupt in the SweRV Core. However i am able to configure the PIC by the help of documentation provided in the doc folder but i am facing an issue. I have configure the source 2 for the external interrupt when the interrupt is asserted in the core the core is jumping to the trap vector code successfully but the claim id is not getting save in the MEIHAP CSR due to which my code is not jumping at the correct ISR it is jumping at the base address of the interrupt vector table.

I'm adding support for SweRV EL2 in SweRVolf. It seems to run fine except for the debug interface. I can read and write RAM but after trying to access device memory through the debugger there's an error messsage about failed abstract commands and then I'm losing connection. This might very well be something that is not correctly hooked up on my side, but I'm wondering about the state of the debug support in EL2. We recently made some changes in how OpenOCD talks to SwerRVolf with EH1 1.8+. Are these changes aligned in the latest EL2 version as well or do I need special handling?

At the integration wrapper level the module containing the ICCM/DCCM SRAM’s is implemented with the el2_mem_if interface and modport: top​

The //mytopdesign// module does not define a modport for the el2_mem_if​
This leads to compile issues through Design Compiler.​

Ie. ​
Warning: In design 'mytopdesign_ccm_sram_wrap_I_el2_mem_export_el2_mem_if_top_', output port 'el2_mem_export.dccm_bank_dout[0][0]' is driven from the outside. (LINT-64)​

One solution that worked on our side:​
Explicitly define two interface buses on mytopdesign with “swerv_iccm/swerve_dccm” modports​
Pushing these two interfaces all the way down to the el2_lsu

Hi,
I saw these lines in el2_ifu_bp_Ctl.sv
https://github.com/chipsalliance/Cores-SweRV-EL2/blob/7045b803cab825bc3bb3dbca0cb019e55098acc4/design/ifu/el2_ifu_bp_ctl.sv#L669-L692

What is the difference between btb_rd_addr_p1_f and btb_rd_addr_f?
Similarly, the difference between btb_bank0_rd_data_way0_p1_f and btb_bank0_rd_data_way0_f?
Also, if anyone could illustrate the for loop and if statement.

The file el2_pic_ctrl.sv contains a 4-bit logic called "mask", which is undriven. This results in X data being driven on picm_rd_data_in and subsequently corrupts the contents of internal PIC registers. How is mask intended to be set? I see the associated enable signal "picm_mken" assert during PIC register accesses.

Hi,

I am trying to synthesize the code for EL2 and when i try to read in the file "el2_param.vh" as an include file,
i get error at the first line as the compiler is not able to understand the code for the parameter as below.

parameter el2_param_t pt = '{

It gives the following error :
7 Error: /ic/dump/rahul.sharma/RISC-V/Cores-SweRV-EL2/WORK/snapshots/default/el2_param.vh:1: Syntax error at or near token 'el2_param_t': expecting default value in local parameter. (VER-294)
8 Error: /ic/dump/rahul.sharma/RISC-V/Cores-SweRV-EL2/WORK/snapshots/default/el2_param.vh:1: Syntax error at or near token 'pt'. (VER-294)

I would appreciate if you could help me with the same and guide me as to how i can synthesize this code.

Thanks,
Rahul.

el2_param.txt

Hi，
I am puzzled why the DMA_ID is set to 1. Can I change it myself? How to change if possible

BR

Hi,
Is there a script to create a rom to the EL2 from a hex file?
Thanks