Comments (6)
I am writing 32'h00000010 on 0xB80 (address of mycylel). Am I following the correct direction?
from cores-veer-el2.
it's designer's leftover to debug his stuff, I'm not sure about mcycle reference there , but you need to provide DUMP_BTB_ON define to compile this code...
from cores-veer-el2.
Yes, I had noticed that later. Can you let me know about how I can set this define DUMP_BTB_ON
. I can't find this define other than el2_ifu.sv
.
from cores-veer-el2.
add
define DUMP_BTB_ON in the beginning of the el2_ifu.sv file. or add
+define+DUMP_BTB_ON` in your simulator compile command or in testbench/flist file
from cores-veer-el2.
need to `define ... in the el2_ifu.sv file . BTW, you don't need to write to mcycle in your test.
from cores-veer-el2.
I have tried both ways but it didn't work
from cores-veer-el2.
Related Issues (20)
- Compilation fails HOT 3
- compile fail with TEST=dhry HOT 1
- Swerv RISC V HOT 2
- SRAM instance export HOT 2
- Remove (or make optional) the JTAG IDCODE command HOT 6
- Export ECC violation signals to the top level as status outputs
- Add support for DMI export to system
- Synthesis issue due to perr_dat_ff signal
- Improve readability and usability of common_defines.vh generated file
- UCR in synthesis
- Caliptra JTAG TdoEn missing output HOT 2
- CDC Error HOT 1
- LHS lesser than RHS : el2_ifu_mem_ctl.sv : ic_debug_way
- Simulation hits max cycle count for dhry, cmark_iccm, cmark_dccm HOT 11
- Does this design work with VCS/Cadence/Mentor simulators after memories were moved from design to tb_top? HOT 2
- Error while build through "make irun" HOT 7
- FuseSoC core description file is missing
- Request to review Lint Issues in Veer RTL HOT 2
- Relation between Core reset(rst_l) and dbg_rst_l
- EL2_DMA_CTRL.sv AXI interface the burst length mode, awlen & arlen is not used, it is Error ?
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