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gk17544's Projects

aes icon aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes-1 icon aes-1

Advanced Encryption Standard (AES) SystemVerilog Core

aescrypt-android icon aescrypt-android

Simple API to perform AES encryption on Android. This is the Android counterpart to the AESCrypt library Ruby and Obj-C (with the same weak security defaults :( ) created by Gurpartap Singh. https://github.com/Gurpartap/aescrypt

ahb2 icon ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

axi-uvm icon axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

chisel icon chisel

Chisel is a collection of LLDB commands to assist debugging iOS apps.

chisel3 icon chisel3

Chisel 3: A Modern Hardware Design Language

core-v-verif icon core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

corundum icon corundum

Open source FPGA-based NIC and platform for in-network compute

cv32e40p icon cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6 icon cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

darkriscv icon darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

i2c icon i2c

I2C controller core

litecan icon litecan

FPGA-based lightweight CAN bus controller.

logic icon logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

opentitan icon opentitan

OpenTitan: Open source silicon root of trust

openwifi icon openwifi

open-source 802.11 WiFi baseband chip/FPGA design

platformio-core icon platformio-core

PlatformIO is a professional collaborative platform for embedded development :alien: A place where Developers and Teams have true Freedom! No more vendor lock-in!

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