Comments (2)
alexforencich
commented on June 1, 2024
Best option at the moment is to use the MAC from this repo in combination with the (free-of-charge) Xilinx 1G PCS/PMA core. See the VCU108 or VCU118 example designs for how to wire this up. Eventually I'll probably have a 1G PCS/PMA in this repo as well, but I don't have a timeline for that at the moment.
from verilog-ethernet.
Beauxrel
commented on June 1, 2024
I'll give it a try and drop my results here.
from verilog-ethernet.
Related Issues (20)
- NetFPGA_SUME for kintex ultrascale HOT 2
- There is no data return in ZCU106 example design HOT 2
- PHY MAC latency HOT 1
- Bug in ssio_sdr_in_diff.v
- Can this IP support 100G Ethernet? HOT 1
- Does this 10G ethernet library use pause frames for flow control? HOT 4
- Misalignment/Deadlock in udp_checksum_gen_64.v
- VCU 128 Support! HOT 3
- ExaNIC_X10 HOT 4
- UDP flow
- UDP flow HOT 1
- How To Trigger ARP Mechanism? HOT 2
- Can this design be validated on Alveo u50 card ? HOT 9
- How to simulate and test the verilog-ethernet design? HOT 6
- Unreachable code in ip_eth_tx_64.v HOT 1
- Is there a block diagram available for the UDP echo server design ?
- How to download and install Icarus Verilog in linux environment? HOT 1
- `test_ip_eth_tx_64.py` hangs HOT 4
- Jumbo Frame Support - Not Working HOT 2
- SGMII design in Stratix 10 using Gx bank HOT 6
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