NetFPGA_SUME for kintex ultrascale about verilog-ethernet

[alexforencich]

Why not start with an example design for Kintex Ultrascale, such as the ExaNIC X10? (or the X25 for UltraScale+)

[SrodinW]

I got the right clock frequency txusrclk_out2 for mac and data. and i can send to host PS, but i have broblems with pcs layer(local fault) and my host had fdir_miss and rx_packet_errors on udp.
i just started working with fpga and some things don't understand.
why in project ExaNIC X10 for kintex ultrascale don't use ip for pcs\pma(10g ethernet pcs\pma) or it's include in ip gtwizard?
when i generate ip gtwizard, i don't uderstand when i should use full or only channel..
and if i use 10g-base-r data 64 bit, then gtrefclk should be156.25(asynchr 64/66b), right? it isn't depend on gth or gty i use?