Comments (6)
Run the tests by running "make" in the appropriate directory (each test case is in a folder with a makefile and a python script). If you want to look at waveforms, run "make WAVES=1". This should produce an fst file that can be opened in gtkwave.
from verilog-ethernet.
Thanks Alex, I ran the tests in cocotbext-eth->eth_mac, gmii, gmii_phy, mii, mii_phy, ptp_clock, ptp_clock_sim_time, rgmii, rgmii_phy, xgmii.
How is the DUT connected to these tests? I see that each of these modules have a ".v" file with only IO ports. I was expecting the "fpga_au50.v" to be my DUT in the tests.
Also, in what sequence should I run these tests to understand the flow of TX and RX data?
from verilog-ethernet.
I invoked the behavioral simulation after loading the fpga.xpr, However the simulation in the waveform does not generate any clock, the mmcm_locked remains "0" and the qsfp_tx_n[3:0], qsfp_tx_p[3:0], qsfp_rx_n[3:0], qsfp_rx_p[3:0] is in "z" state.
Note: I am not able to add any screenshot of waveform
from verilog-ethernet.
The Alveo example design testbench is here: https://github.com/alexforencich/verilog-ethernet/tree/master/example/Alveo/fpga_25g/tb/fpga_core
from verilog-ethernet.
The Alveo example design testbench is here: https://github.com/alexforencich/verilog-ethernet/tree/master/example/Alveo/fpga_25g/tb/fpga_core
Hi Alex,
When I try to run simulation using "make WAVES=1", I get the following error. Am I missing anything in the setup?
ERROR: results.xml was not written by the simulation!
make[1]: *** [/home/[email protected]/anaconda3/lib/python3.9/site-packages/cocotb/share/makefiles/simulators/Makefile.icarus:96: results.xml] Error 1
make[1]: Leaving directory '/home/[email protected]/verilog-ethernet/example/Alveo/fpga_25g/tb/fpga_core'
make: *** [/home/[email protected]/anaconda3/lib/python3.9/site-packages/cocotb/share/makefiles/Makefile.inc:40: sim] Error 2
from verilog-ethernet.
The issue was with "scapy" that needs to be installed as most testcases uses scapy libraries. After installing scapy I was able to run the testcases
from verilog-ethernet.
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