Comments (6)
Unfortunately I don't have any soft IP for SGMII/1000BASE-X at the moment, so I recommend looking at Intel's soft IP. Presumably they have something for a 1G PCS/PMA, but I'm not sure if it's free-of-charge like the Xilinx one. I am looking at putting together soft IP for 1G to support dynamic switching between 1G and 10G as well as to support WR, but I have no timeline for that at the moment.
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I tried using the Intel Triple Speed Ethernet Ip but it only provides option for LVDS Serdes and not for GX bank. Can you help me how i can integrate the TBI interface with native transceiver IP.
I have configured the TSE as SGMII MAC and PCS. For the PMA what can i use?
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Hi Alex,
Waiting for your valuable suggestion on this. Please help me with the design generation.
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Buy, build, or contract?
Buy: Looks like https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/1g-10g.html or https://www.intel.com/content/www/us/en/partner/showcase/offering/a5b3b0000004cS2AAI/ethernet-pcs-1g25g.html would probably work. There are probably more options. Not sure about pricing on those - if you're affiliated with a university, you can probably get a license for the Intel 1G/10G core without too much trouble.
Build: I might be able to offer some guidance if you're potentially interested in building an open-source 1G PCS/PMA from scratch for inclusion in this repo.
Contract: I might also be able to build such a core under contract. I'm planning on implementing it anyway eventually, but currently I do not have a timeline for that.
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i Would like to build
from verilog-ethernet.
Alright then, join the corundum zulip (https://corundum.zulipchat.com) and we can discuss in more detail.
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Related Issues (20)
- There is no data return in ZCU106 example design HOT 2
- PHY MAC latency HOT 1
- Bug in ssio_sdr_in_diff.v
- Can this IP support 100G Ethernet? HOT 1
- Does this 10G ethernet library use pause frames for flow control? HOT 4
- Misalignment/Deadlock in udp_checksum_gen_64.v
- VCU 128 Support! HOT 3
- ExaNIC_X10 HOT 4
- UDP flow
- UDP flow HOT 1
- How To Trigger ARP Mechanism? HOT 2
- Can this design be validated on Alveo u50 card ? HOT 9
- How to simulate and test the verilog-ethernet design? HOT 6
- Unreachable code in ip_eth_tx_64.v HOT 1
- Is there a block diagram available for the UDP echo server design ?
- How to download and install Icarus Verilog in linux environment? HOT 1
- `test_ip_eth_tx_64.py` hangs HOT 4
- Jumbo Frame Support - Not Working HOT 2
- Bug in udp_checksum_gen
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