Constant and inverter "replication" during packing about vtr-verilog-to-routing

[vaughnbetz]

Couldn't (and shouldn't) this be done at the end of synthesis? If the primitive being fed by a signal can handle programmable inversion, then remove the inverter.
LUTs -> remove (already done I believe)
FF enables etc: -> if the FF has a programmable inverter on it, remove the inverter

I think the remaining case you're trying to solve is if you have a programmable inverter at the cluster level, but not the primitive level (e.g. maybe you can invert an enable for the entire cluster?). I think that should be doable by putting an inverter in the cluster architecture definition, with interconnect that allows it to drive the enable signal or the enable input pin to drive it directly.

Am I capturing the situation correctly?

[rs-dhow]

Yes, the problem is if the "perverter" is at the cluster level. Imagine a signal goes uninverted to EN on some flops and inverted to other flops (in the original design). Each cluster (CLB) supports say 4 enables, which could be any mixture of 4 enables to 2 phases of 2 enables. (UltraScale+ is similar to this.) The "phase needs" of each FF interact with the clustering decisions (it's a signal/phase counting problem, maybe related to current pin counting), which is why this can't be done in synthesis. Now, if I put the inverter in the cluster level of the arch definition, then I end up back at the replication problem I started with. Make sense? Thanks.