Missing Output Port in BLIF File Generation Using ABC about vtr-verilog-to-routing

[kimiatkh]

Hi @vaughnbetz ,

This was the ABC-related issue I was facing in multi-clock circuit processing. To avoid cross clocking optimization, VTR preprocesses the input netlist, hiding all clock domains except for one at each iteration by turning all the latches of all other clocks into black boxes. If we have a case where the output of the register is directly driving an output port, when the latch turns into the black box and goes through the ABC run, the output port gets removed from the netlist. If all the outputs are registered, in fact, no outputs are left by the time all the passes are done. Above is the description of the issue.
I was not sure, however, who are the related people to include on this issue. Could you please include the people who might be able to help with this?

Thanks,