Comments (2)
I am 100% in support of this change! I also agree that the CI should not run if there are non-functional changes.
A potential issue you may run into is that there are required tests in our PR flow (sets of tests which must succeed in order for the code to be merged in). If the CI does not run for documentation changes, the PR may never be merged since it did not pass the required tests. I am not sure the best way to resolve this issue, but it should be resolved.
Also, maybe GitHub handles this on its own! I would not be surprised if there are some checks in place to allow PRs to merge if they specifically request not to run!
from vtr-verilog-to-routing.
Some tests won't run, so we'll have to merge despite that. Let's go with that for now ... too bad we can't mark the docs as needing a smaller list of checks.
from vtr-verilog-to-routing.
Related Issues (20)
- Update documentation for 3D arch switches
- Test rr-graph write out and read in with a 3D architecture.
- Missing Output Port in BLIF File Generation Using ABC HOT 1
- Constant and inverter "replication" during packing HOT 2
- Remove has_path_to_sink HOT 1
- high fanout routing to heap code -- only count CHANX and CHANY nodes to determine if enough has been added. HOT 5
- Loosen the minimum channel width and related metric pass characteristics for small circuits HOT 1
- See if simplifying the placement cost function slightly would speed up placement.
- Document how to build for debugging HOT 2
- Missing documentaion for some 3D-related tags and fields in the architecture reference
- [Route] Precision Issues in the Connection Router HOT 6
- Relax when router lookahead issues warnings for failure to find sample locations HOT 5
- [CI] Nightly Test Failures HOT 2
- Passing only Fc max to pin to track map function HOT 5
- Placement Internals Document
- Placement `channel_width_fac`
- [CI] Investigating CI Runners HOT 5
- Remove +1 from wirelength estimate
- Fc_override Not Parsed Correctly HOT 1
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from vtr-verilog-to-routing.