Error in delay when LUT operates as wire about vtr-verilog-to-routing

[kmurray]

Reported by JasonKaiLuu on 2012-06-04 21:51:28

• Labels added: Module-VPR

[kmurray]

Just a matter of copying over whatever delay annotations the user put in for the LUT
over to the wire.  

This brings up an interesting point.  A LUT typically has different delays based on
which input is used.  The fastest LUT input can be a few times faster than the slowest
LUT input.  So I should transition the current breadth hop router to a min delay router
to take advantage of this effect when the LUT is operating as a wire.  We need to do
something about LUT input swapping for the normal LUT case.

Reported by JasonKaiLuu on 2012-06-05 19:21:54

• Status changed: Fixed