Comments (5)
This is something I would use as well. It makes the initial portion of the routing graph output a more complete description of the architecture for routing purposes. Note that there is no RELIABLE way of deducing the intended (non-clipped) length of a segment over arbitrary array sizes. Thanks.
from vtr-verilog-to-routing.
Agreed, let's do this. @amin1377 says he can get to it in the not-too-distant future.
from vtr-verilog-to-routing.
That's great news. Thank you.
from vtr-verilog-to-routing.
Thanks @amin1377. Your approach of always including it in output, and checking it in input if present, is the correct one. Current VPR behavior also means a CHANX/CHANY node should always have length(node) <= length(node's segment id), with equality when the node is not near the array edge and inequality when the node is clipped by the array edge since it otherwise would stick outside the edge. Thanks again.
from vtr-verilog-to-routing.
Thank you! @amin1377
from vtr-verilog-to-routing.
Related Issues (20)
- Make a short coding style guide in the VTR developer guide
- vtr optional documentation showing up at the top of vtr::vector and vtr::vector_map documentation HOT 1
- redundant adders when synthesizing addition with full adders HOT 2
- Placement Constraints not working HOT 8
- [Logging] Incorrect LUT Sizes Circuit Statistic Printing
- [Logging] Overly Verbose Log Messages When Building RRGraph HOT 3
- [Netlist] Potential Issue When Re-Creating Elements in Atom and Clustered Netlists HOT 2
- if VPR have routing constraint like Xilinx fixed routing
- 3D switch block updates & commenting
- ./kernel/yosys.h:42:10: fatal error: 'map' file not found HOT 3
- [IPA] MVP to manually test vpr --server mode HOT 3
- [Build] VTR Fails to Build on ASSERT_LEVEL=4 HOT 2
- Issue with Multibit Adder in VTR flagship architecture
- VTR throws warning for shorted SB connections
- (Caused by io location changed)The suspicious detour phenomenon that significantly reduces the slack
- Multibit Adder Architecture Failure
- VTR seems to struggle with being smart about how it packs into memories
- Improve 3D switch block commenting and move command line option to arch file
- Packing Devices from Two Separate Parts of a Netlist into a Single CLB
- CLBs Positioned Far from IOs
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