Comments (2)
Comment from @rs-dhow
May be able to handle this by ensuring we have different modes for arithmetic, 5 vs. 6-LUT etc. and never declare more inputs than can be swapped on the LUT in that mode.
from vtr-verilog-to-routing.
Decided this probably isn't needed.
from vtr-verilog-to-routing.
Related Issues (20)
- high fanout routing to heap code -- only count CHANX and CHANY nodes to determine if enough has been added. HOT 5
- Loosen the minimum channel width and related metric pass characteristics for small circuits HOT 1
- See if simplifying the placement cost function slightly would speed up placement. HOT 1
- Document how to build for debugging HOT 2
- Missing documentaion for some 3D-related tags and fields in the architecture reference
- [Route] Precision Issues in the Connection Router HOT 6
- Relax when router lookahead issues warnings for failure to find sample locations HOT 6
- [CI] Nightly Test Failures HOT 2
- Passing only Fc max to pin to track map function HOT 8
- Placement Internals Document
- Placement `channel_width_fac`
- [CI] Investigating CI Runners HOT 5
- Remove +1 from wirelength estimate HOT 1
- Fc_override Not Parsed Correctly HOT 1
- Koios Benchmarks Failing With Flat Routing HOT 1
- VPR warning verbosity with timing analysis on and custom routing graphs with isolated clock routing
- VTR format checking / auto-format not checked by CI?
- Make a short coding style guide in the VTR developer guide
- vtr optional documentation showing up at the top of vtr::vector and vtr::vector_map documentation HOT 1
- redundant adders when synthesizing addition with full adders HOT 2
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