Comments (4)
To clarify, the bug is due to the fact that the 'direct' and 'mux' types are mixed,
instead of grouped. Mixing will not always cause the bug - only certain orderings
will do so.
This is a known issue in past versions of ezxml.
Reported by jeffrey.goeders
on 2012-05-08 00:48:02
from vtr-verilog-to-routing.
Actually, I mistakenly thought I tested with the new ezxml. In fact I did not.
I didn't realize we had modified the ezxml.c file. Perhaps our modifications are the
source of the bug. Diffing the latest version of ezxml with our version, I only notice
the locations that we have changed.
For now we should just be careful in how we write architecture files.
Reported by jeffrey.goeders
on 2012-05-08 18:44:50
from vtr-verilog-to-routing.
When I get the newest ezxml, add in the line numbers update, and run, it seg faults.
Will probably need to do what Ted Campbell did to fix the numerous memory access bugs
in ezxml if we want to use the newest version.
Reported by JasonKaiLuu
on 2012-05-09 20:23:17
from vtr-verilog-to-routing.
Fixed in 33e01c8, as ezxml has been replaced with the more robust pugixml.
from vtr-verilog-to-routing.
Related Issues (20)
- Run-flat on Koios Benchmark HOT 1
- Router Lookahead File Extension Error Handling HOT 3
- Change RRG storage to keep (drive pt, direction) instead of (start, end)
- Try setting first_iter_pres_fac to a value > 0 HOT 1
- Designs with many different wire types fail at certain channel widths with an arithmetic exception
- Clean up rr_node_route_inf HOT 4
- Add wire length attribute to RR graph output XML when using "--write_rr_graph" option
- CI Test Failures on Master HOT 3
- Failed to build target 'libarchfpga' HOT 1
- Disabling CAPNPROTO Crashes Build
- clang/LLVM-17 build HOT 4
- Remove Warnings in VTR CI Builds
- Parmys fails to properly handle multipliers with unequal input widths HOT 5
- Primitive input pin permutability should be more general HOT 1
- 3d switch block code, architecture files & reg tests
- [Documentation] Missing Documentation on `--router_profiler_astar_fac` HOT 7
- Turn on faster place delay matrix loader by default
- vpr placement algorithm HOT 2
- Giant distance from initial placing and routing solution to a better one VTR could have found.
- Document how to use Perf for profiling with vpr
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