Comments (1)
The comments in issue #68 describes the requirements and steps for adding support for a new FPGA. At this time, we do not have plans to add support for any additional platforms, but it is possible if the requirements are met, and we welcome external contributions. Please let me know if you have any additional questions.
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Related Issues (20)
- Is this project dead HOT 1
- Vivado HLS failed to package/export IP due to Xilinx's bug HOT 2
- A Minor Mistake in Documentation About Setting Environments for CentOS 7 HOT 1
- X11 error for non-root users on CentOS HOT 1
- Reading Clock cycles HOT 1
- How to change the clock frequency of a SoC prototyped on a xc7v2000t profpga
- P2P only works if accelerators are set to operate in non-coherent mode HOT 1
- State of ZCU102 support HOT 2
- Cannot find required source file '*_localmem_asic.sv' HOT 3
- Xcelium cannot simulate for single-core(Ibex) SoC using the repo configuration from official Docker image HOT 2
- Problem running simulation in tutorial for designing a single core soc HOT 3
- Internal compiler error when trying to build risc-v toolchain for ariane processor
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- Can't Program Xilinx VC707 Board in Single-Core SoC Tutorial HOT 4
- Missing NV_NVDLA.verilog and Collecting generated RTL files HOT 4
- How to use the debug signal of an accelerator
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