Comments (4)
-
You can run the command
make genus-setup
from your SoC design folder. This will create two scripts inside a folder calledgenus
:srcs.tcl
andincdir.tcl
. These contain all of the RTL sources and include directories, respectively. -
Did you run
make NV_NVDLA
before running the simulation?
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Thanks for your swift reply Jzuckerman!
You can run the command make genus-setup from your SoC design folder. This will create two scripts inside a folder called genus: srcs.tcl and incdir.tcl. These contain all of the RTL sources and include directories, respectively.
At which step during ESP flow, should I ran the make genus-setup
to get the complete RTL filelist?
Did you run make NV_NVDLA before running the simulation?
I wish to try a single-core SoC design with the NVDLA accelerator and below is my expected ESP flow:
- Is the "caches" option mandatory when using NVDLA? If I choose to use "ESP RTL" implementation for the caches, are all of the caches files produced in .sv format?
make NV_NVDLA
:
- Is this make target needed to run evertime?
make sim
andrun -all
:
- Can these two simulation steps be skipped since I only have VCS simulator at hand?
make vivado-syn
make soft
andmake linux
:
- The first command will produce prom.bin and systest.bin while the latter one produce the Linux image linux.bin. Can I put them into one SD card and boot the system automatically when clock and reset is on? Besides, it is said that the SoC runs at 50MHz but my FPGA board can only run 10MHz in maximum. Will the reduction of clock frequency cause problems?
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In the third-party accelrator tutorial, authors mentioned that we need the list(.verilog and .sverilog) of hw files. However, they didn't provide .verilog and .sverilog, which make the compiler fail to find the relevant hardware sources files for NVDLA.
@jzuckerman Could you please provide an example file(NV_NVDLA.verilog) for us? Or tell us how to list all hardware source files in correct grammar in .verilog.
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The NV_NVDLA.sverilog is empty because there is no System Verilog in the design. The NV_NVDLA.verilog is copied from one of these two files (https://github.com/sld-columbia/esp/tree/dev/accelerators/third-party/NV_NVDLA/config) when you run make NV_NVDLA, depending on whether you are targeting an FPGA or an ASIC.
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Related Issues (20)
- Is this project dead HOT 1
- Vivado HLS failed to package/export IP due to Xilinx's bug HOT 2
- A Minor Mistake in Documentation About Setting Environments for CentOS 7 HOT 1
- X11 error for non-root users on CentOS HOT 1
- Reading Clock cycles HOT 1
- How to change the clock frequency of a SoC prototyped on a xc7v2000t profpga
- P2P only works if accelerators are set to operate in non-coherent mode HOT 1
- State of ZCU102 support HOT 2
- Cannot find required source file '*_localmem_asic.sv' HOT 3
- Xcelium cannot simulate for single-core(Ibex) SoC using the repo configuration from official Docker image HOT 2
- Problem running simulation in tutorial for designing a single core soc HOT 3
- Internal compiler error when trying to build risc-v toolchain for ariane processor
- Trying to make single-core SoC tutorial work for Nexys A7-100T HOT 2
- Can't Program Xilinx VC707 Board in Single-Core SoC Tutorial HOT 4
- Alternatives of listed FPGA boards HOT 1
- How to use the debug signal of an accelerator
- NVDLA does not work with Leon3 on 64-bit DMA NoC
- Bootloader hangs on ESP soc includes nvdla on VCU128 HOT 1
- Clarification on the ESP NoC HOT 1
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