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The gem5 files situated in Simulators/gem5 are not compatible with the current commit of gem5.
Also, when used March 1 st 2017 commit, how do we build as the command in README causes an error unrecognized memory type NVMainMemory.

When reading the paper(NVMain 2.0), noticed that nvmain can support bank-group refresh as in DDR4 in chapter 2.3. But I don't know how to configure it for DDR4?

I am working on the DDR4 simulation, but NVmain only have the DDR3 config template, I grep the source code and don't find the "bankgroup" keywords, so I wonder using the "subarray" replace "bankgroup"? I was really confused.

The link to nvmain wiki page, mentioned in the readme, "http://wiki.nvmain.org/" is no longer working.

I see that trace file can be generated by printtrace. config with running gem5, but I can't get it.

I'v added a config file called PCM_ISSCC_2012_8GB.config into nvmain/Config/PCM_ISSCC_2012_8GB.config. And then I run

./build/X86/gem5.opt configs/example/se.py -c tests/test-progs/hello/bin/x86/linux/hello --caches --l2cache --mem-type=NVMainMemory --nvmain-config=../nvmain/Config/PCM_ISSCC_2012_8GB.config

It tells me like this:

Global frequency set at 1000000000000 ticks per second
NVMainControl: Reading NVMain config file: ../nvmain/Config/PCM_ISSCC_2012_8GB.config.
0: system.remote_gdb: listening for remote gdb on port 7000
NVMain: GlobalEventQueue: Added a memory subsystem running at 400MHz. My frequency is 2000MHz.
NVMain Error: unrecognized address mapping scheme: R:RK:BK:CH:C
NVMain: the address mapping order is
Sub-Array 1
Row 6
Column 0
Bank 4
Rank 5
Channel 3
'.Main: Unknown memory controller `FRFCFS
gem5 has encountered a segmentation fault!

But I found the FRFCFS in the file already and when I use the PCM_MLC_example.config(the system already has at the beginning), it uses the FRFCFS and there's no bug.