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An open-source 32-bit RISC-V soft-core processor

Home Page: https://riscv-atom.readthedocs.io

License: MIT License

Makefile 3.27% Verilog 19.82% SystemVerilog 1.37% C++ 40.01% Assembly 2.01% C 20.25% Python 7.55% Shell 0.31% Tcl 5.14% Dockerfile 0.27%
riscv processor cpu riscv32 microcontroller embedded fpga core risc-v soc

riscv-atom's Issues

RV32-M extension implementation

Hello,
We have tried to implement RV32M extension instruction, please have a look. The extension instruction also passes riscv-test benchmark. If you want your riscv-atom to support RV32M, you can look at out code as an reference.

The finished version is in branch stable . Here is the Link 1, Link 2.

Best Regards ๐Ÿ‘

Redundancy in makefile

There is a redundancy in the makefile while declaring Verilog files for the targets - atombones and hydrogensoc. Clearly these targets have some files that are needed by both and some files that only one of the targets requires.

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