saursin / riscv-atom

An open-source 32-bit RISC-V soft-core processor

RISCV-Atom

RISC-V Atom is an open-source soft-core processor platform targeted for FPGAs. It is complete hardware prototyping and software development environment based around Atom, which is a 32-bit embedded-class processor based on the RISC-V Instruction Set Architecture (ISA).

Key highlights of the RISC-V Atom projects are are listed below:

• Atom processor implements RV32IC_Zicsr ISA as defined in the RISC-V unprivileged ISA manual.
• Simple 2-stage pipelined architecture, ideal for smaller FPGAs.
• Wishbone ready CPU interface.
• Support for RISC-V interrupts and exceptions.
• Interactive RTL simulator - AtomSim.
• In-house verification framework - SCAR.
• FPGA-ready SoC implementation - HydrogenSoC.
• Tiny libc like standard library - libcatom.
• Wide range of example programs.
• Open source under MIT License.

To checkout this project, Please refer to the Getting Started Guide. Use the dev branch, if you like to see the latest additions to the project

Useful Links

1. Project Website
2. Project Documentation
   • Getting Started Guide
   • Examples Guide

License

This project is open-source under MIT license!

riscv-atom's Issues

Atomsim source code needs documentation

Add runtime-disassembly feature in atomsim

Toolchain install script might not work.

Instead of installing toolchain in system.
Just have it downloaded in workspace.
It will be easy for system maintenance and cleaning up.

gpio.c not fit for Atombones target

make libs fails with atombones target because GPIOs are not present in atombones and hence gpio.c compilation shows error.

Different streams for program output and atomsim verbose info

All verbose information should be printed on stderr stream while the program's output should be printed on the stdout. Therefore one can easily route them to two different files if needed.

RV32-M extension implementation

Hello,
We have tried to implement RV32M extension instruction, please have a look. The extension instruction also passes riscv-test benchmark. If you want your riscv-atom to support RV32M, you can look at out code as an reference.

The finished version is in branch stable . Here is the Link 1, Link 2.

Best Regards 👍

Running AtomSim without --vuart option causes segmentation fault

Add more SCAR tests

Use RISCOF for ISA compliance testing

• Remove old makefile-based compliance verification
• Use the new RISCOF framework for compliance testing

Redundancy in makefile

There is a redundancy in the makefile while declaring Verilog files for the targets - atombones and hydrogensoc. Clearly these targets have some files that are needed by both and some files that only one of the targets requires.