ros-acceleration / community Goto Github PK

Follows from #9 and #20.

Goal of this ticket is to merge upstream acceleration kernels in two forms a) binaries (bitstream) and b) source code, so that users can leverage them directly from their computational graphs in a simplified manner.

Candidate: image_pipeline

NOTE: This ticket has moved to https://github.com/robotperf.

This ticket tracks the progress of the RobotPerf subproject of the ROS 2 Hardware Acceleration Working Group. Content will be updated as we progress. In time, a repository will branch out of this effort and to its own organization containing additional resources. Expectation however should be for the initial discussion to remain in here for organizational purposes. You can send feedback about this and/or participate by contacting here.

RobotPerf project

Goal: Design and develop a reference benchmarking suite that is used to evaluate robotics computing performance with ROS 2.

RobotPerf also aims to become a consortium of robotics leaders from academia, research labs, and industry whose mission is to build fair and useful robotics benchmarks that are technology agnostic, vendor-neutral and provide unbiased evaluations of robotics computing performance for hardware, software, and services—all conducted under prescribed conditions.

Rationale and motivation

Benchmarking is the act of running a computer program with a known workload to assess the program's relative performance. In the context of ROS 2, performance information can help roboticists design more efficient robotic systems and select the right hardware for their robotic application. It can also help understand the trade-offs between different algorithms that implement the same capability, and help them choose the best approach for their use case. Performance data can also be used to compare different versions of ROS 2 and to identify regressions. Finally, performance information can be used to help prioritize future development efforts.

The myriad combinations of robot hardware and robotics software make assessing robotic-system performance in an architecture-neutral, representative, and reproducible manner challenging. RobotPerf attempts to provide a reference benchmarking suite that is used to evaluate robotics computing performance built with ROS 2.

Why ROS 2

Robot behaviors take the form of computational graphs, with data flowing between computation Nodes, across physical networks (communication buses) and while mapping to underlying sensors and actuators. The popular choice to build these computational graphs for robots these days is the Robot Operating System (ROS)¹, a framework for robot application development. ROS enables you to build computational graphs and create robot behaviors by providing libraries, a communication infrastructure, drivers and tools to put it all together. Most companies building real robots today use ROS or similar event-driven software frameworks. ROS is thereby the common language in robotics, with several hundreds of companies and thousands of developers using it everyday. ROS 2 ² was redesigned from the ground up to address some of the challenges in ROS and solves many of the problems in building reliable robotics systems.

ROS 2 presents a modern and popular framework for robot application development most silicon vendor solutions support, and with a variety of modular packages, each implementing a different robotics feature that simplifies performance benchmarking in robotics.

Sponsorship

The project is open to sponsorships and collaborations. For sponsoring the RobotPerf project contact here.

Milestones

(to be described)

Originally posted by @soufien-gdaim in #1 (comment)

Hi all,
I have the same error when I tried the Emulation SW, a

nd I didn't understood how can I solve this error even after I read your comments. so can you please tell me how can I solve this error. To built this project I use Vitis 2020.2, petalinux 2020.2 with zc702 card (zynq7000).
With another project (Zybo7, I download the a prebuilt project), I didn't have problems, I can do Emulation sw, Emulation hw and hardware without any problems.
Attached are the Vitis capture

.

An extension for colcon-core to include Hardware Acceleration capabilities and simplify acceleration flows. Initially targeting the following mechanisms:

• selection across embedded targets (capable/not-capable of doing hardware acceleration) easily
• list available embedded targets
• simplify configuring Linux kernel (provide at least two default configurations)
• simplify configuration of type 1 hypervisors (e.g. Xen)
• integrate emulation capabilities (to cope with the lack of hardware availability) directly in the colcon flows
• other utilities to manage embedded (mount, umount, extract ramdisks from raw disk images, etc.)

This ticket tracks the progress of the Robotics MCU subproject of the ROS 2 Hardware Acceleration Working Group. Content will be updated as we progress. In time, a repository will branch out of this effort containing additional resources. Expectation however should be for the initial discussion to remain in here for organizational purposes. You can send feedback about this and/or participate by contacting here.

Robotics MCU project

Goal: Design and develop an open source software and hardware robotics microcontroller unit (Robotics MCU) powered by RISC-V that delivers lower latency and additional real-time capabilities in ROS 2 MCU interactions. The ultimate objective of the project is to design an MCU that contains a native ROS 2 hardware implementation.

Project's technical name: robo-v-mcu.

Rationale

A microcontroller (MCU for microcontroller unit) is a small computer that contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals. MCUs are typically more specialized than microprocessors (MPUs, sometimes also known as Application Processing Unit or APUs), as they integrate functions which are specific to a certain domain or area of application. Though microcontrollers are generally accepted as programmable specialized devices, most MCUs used in robotics today have rather general purpose building blocks. There is not much robotics-specific in any of them.

Current popular strategies in robotics for integrating microcontrollers involve complex bridges that break DDS databus interoperability and that introduce undesired delays and much complexity, delivering a hard to optimize and maintain result, namely the micro-ROS project (XRCE-DDS approach). The Robotics MCU project aims to tackle some of the problems identified in the micro-ROS architecture by focusing on 1) enabling ROS 2 direct interoperability from within an open MCU design in the form of a soft-core, 2) performing benchmarks of the resulting design and analyze data together with the micro-ROS approach in both soft and hard-cores, 3) creating a native ROS 2 hardware implementation in an MCU by bringing software layers of the design into IP blocks that can be then transformed into hardware, 4) Customizations of the Instruction Set Architecture (ISA) to optimize ROS 2 operations and 5) prototyping the resulting Robotics MCU design as a hard-core with one of the popular foundries (and currently available programs).

The Robotics MCU subproject will be developed as part of the ROS 2 Hardware Acceleration Working Group and prototyped first into an FPGA and later into a physical chip.

Sponsorship

The project is open to sponsorships and collaborations. For sponsoring the Robotics MCU project contact here.

Technical specs (initial set, may change)

Milestones

• Project announcement and initial planning (this ticket)
• Milestone 1 (ongoing): Robotics MCU as an open RISC-V based MCU design with ROS 2 direct interoperability capabilities (soft-core)
  • phase 1 - hw: CORE-V-MCU adaptation to KR260 (ongoing)
    • 13/12/22: PlanV reported various issues while porting CORE-V-MCU to the target hardware (KR260), looking into those
    • 31/01/23: Issues addressed. Appeared to be glitches while reproducing and flashing things.
  • phase 2 - rtos: FreeRTOS, this might come for free (see demo)
    • 2.1 FreeRTOS validation (see demo)
    • 2.2 Ethernet driver
  • phase 3 - net. stack: lwIP
  • phase 4 - comm. middleware: embeddedRTPS
  • phase 5 - ROS: rmw_embeddedrtps, rmw, rcl, rclc
• Milestone 2: benchmarks of (soft-core) Robotics MCU in an FPGA and comparison with existing alternatives in other soft and hard-cores
• Milestone 3: hardware prototyping the resulting Robotics MCU with a popular foundry/program
• Milestone 4: native ROS 2 hardware implementation by bringing software layers of the design into IP blocks that can be then transformed into hardware (soft-core)
• Milestone 5: customizations of the ISA to optimize ROS 2 operations
• Milestone 6: hardware prototyping 2 the resulting Robotics MCU with a popular foundry/program

Provide reference examples and blueprints for acceleration architectures used in ROS 2 and Gazebo.

Summarizing easily measurable dissemination efforts that happened as part of the HAWG ¹:

Articles and posts in digital media, including robotics communities and social media

YouTube

The objective of this ticket is to discuss and coordinate the upcoming proposal the HAWG will submit for a workshop during ROSCon 2022.

Important aspects:

• deadline: 2022-05-06
• Title (maximum 70 characters)
• Presenter(s) (name and affiliation)
• Summary - for public consumption, used in the program schedule (maximum 100 words)
• Description - outline and goals, for review by the program committee. Describe the intended audience and what resources (if any) would be required. Please be sure to include enough information in your proposal for the program committee to evaluate the above review criteria

Topics desired:

• ROS 2 hardware acceleration (FPGA, GPU and in any other compute substrate)
• Compute architectures in robotics
• Use cases demanding hardware acceleration

Latest draft (being edited based on feedback)

(send feedback bellow)

• Title: ROS 2 Hardware Acceleration Workshop
• Presenter(s):
  • (TBD: compile final list and add presenters)
• Summary: The decline of Moore’s Law and Dennard Scaling limit the performance of ROS computational graphs in traditional CPU computing. This positions hardware acceleration as an important emerging solution to achieve higher performance and power efficiency. To do so, compute platforms must map ROS graphs efficiently to CPUs, but also to specialized hardware including FPGAs and GPUs. This workshop discusses the status of hardware acceleration in ROS 2. We'll summarize the progress of the Hardware Acceleration WG delivering speedups for both single ROS nodes and complete graphs, discuss computing architectures in robotics and present various ROS use cases demanding hardware acceleration.
• Description: WIP

NOTE: This ticket has moved to https://github.com/ros-acceleration/robotic_processing_unit.

This ticket tracks the progress of the Robotic Processing Unit (RPU) subproject of the ROS 2 Hardware Acceleration Working Group. Content will be updated over time. In time, a repository will branch out of this effort containing additional resources. Expectation however should be for the discussion to remain in here for organizational purposes. You can send feedback about this subproject via this form.

The Robotic Processing Unit (RPU)

Definition: A robot-specific processing unit that maps ROS and robot computational graphs efficiently to underlying compute resources including CPUs, FPGAs and GPUs to obtain best performance.

Vision

The vision is that RPUs will empower robots with the ability to react faster (lower latency, higher throughput), consume less power, and deliver additional real-time capabilities with their custom compute architectures that fit best the usual robotics pipelines. This includes tasks across sensing, perception, mapping, localization, motion control, low-level control and actuation.

Antigoal

The initial objective of this subproject is not to design a new physical device. Instead, existing off-the-shelf hardware acceleration development platforms will be used to prototype a robot-specific processing unit that performs best when it comes to ROS 2 and robot computational graphs.

Sponsorship

The project is open to sponsorships and collaborations. For sponsoring the Robotic Processing Unit (RPU) contact here.

Milestones

Milestone 1: first demonstrators - raise awareness

• Robotic Processing Unit (RPU) project announcement
• RFC to receive feedback and interest https://forms.gle/d4rCCoLpx9ciPiau9
• Use cases driving the architecture and the development
  • Perception (image_pipeline and friends)
    • perception_2nodes
    • perception_3nodes
    • Maybe consider a more elaborated graph with multi-processing paths involving more complex CV crunching, e.g. HOG (Histogram of Oriented Gradients)?
  • Navigation
    • Still in dicussions, open to feedback.
• Partition work into demonstrators, prioritize and execute
• Disclose an initial hardware reference design of the Robotic Processing Unit https://github.com/ros-acceleration/robotic_processing_unit
• Disclose benchmarking results and discuss (connected to #10)

• Disclose initial draft of the methodology and discuss with WG
• Hardware acceleration across silicon architectures (comparing results across somewhat equivalent commercial solutions) https://news.accelerationrobotics.com/hardware-accelerated-ros2-pipelines/
• Release paper https://arxiv.org/pdf/2205.03929.pdf

Hi, every body.

I want to choose an appropriate mini pc for my robotic application.
I want to know which part of my mini PC I should spend more money on.
The duty of the mini-pc is mainly to collect data from its I/O and emit the data over ROSnetwork, and maybe in the future, some ROS2 packages will be run on this mini-pc too.

As I know, most ROS packages run on the CPU and RAM, also Localhost, and for external communication nodes, send and receive from the network is mainly handled by the CPU and network card.

Should I spend more on my CPU and RAM, and network card?

Can ROS2 communicate effectively with 10Gb and 25Gb card networks?

Are there any sources that guide me to the bottlenecks in components of computers for implementing ROS2?

Another question is how I should find that sending and proccing data on one local robotics core server and receiving from its server is faster than my computer processing data with my non-efficient algorithm. (due to the physical distance between my computer and the local robotics core server that couldn't be omitted)

Are there any sources to help me to find this type of question?

Task list:

• Describe the benchmarking architecture in a formal manner https://github.com/ros-infrastructure/rep/pull/324/files#diff-f230b6aa06d86bf594d8e431300e453ad7343e8f4b1932252b6d36c62a8b5e0aR203-R267
• Create tracepoint examples for hardware acceleration as a fork of tracetools (fork might get integrated into tracetools in the future if appropriate) https://github.com/ros-acceleration/tracetools_acceleration
  Facilitate testing environments that allow to benchmark accelerators with special focus on power consumption and time.
• Instrument some of the examples at acceleration_examples
  • doublevadd_publisher
  • faster_doublevadd_publisher
• Contributed and disclosed adaptive_component
• Document it step-by-step in a comprehensive manner (pushed to future documentation tickets)
• Provide guidelines and recommendations to further instrument computations engaging with FPGAs and GPUs (stretch goal, might be pushed to future tickets)

Instructions to add a new board to the community.

Follows from #34. Summarizing easily measurable dissemination efforts that happened as part of the HAWG:

Tracking progress

Key milestones

Key articles and posts in traceable digital media

Meeting recordings (YouTube channel)

Goals for 2024

The Hardware Acceleration Working Group continued growing significantly during 2023. Altogether, that is 3 years of continued growth (2021, 2022). Having accomplished most of the initial objectives of the working group when created in 2021, and having supported multiple silicon vendors as part of the The ROS 2 Hardware Acceleration Stack, the working group will focus next on three objectives: the first objective is to continue working on demonstrators and case studies. We generated very exciting results within 2023 that we'll expand during the next year and hopefully disclose publicly. The second objectives will be to build upon the success of the reference FPGA-based ROS 2 implementation for High-Speed Networking and explore other accelerators. Some ideas include bridging between other communication middlewares or even pushing the speed of networking interactions faster. The third objective is to evolve the RobotPerf project, which attracted quite a few contributors already (see RobotPerf paper). Subgoals here would be to create more benchmark releases, add new benchmarking categories (with their corresponding benchmark implementations) and ultimately, expand the project to other communities which could benefit from it, all while remaining ROS-centric.

Altogether, the objectives for the coming year look as follows:

Rationale of this ticket is to define a reference computational graph system for the hardware acceleration WG efforts that should serve as a reference resource for benchmarking purposes (in concert with other efforts including #9).

• Explore Real-Time WG's #9 and evalute fitness
  • seems autoware centric, evaluate fitness from a stack-agnostic perspective as well
• Initial results

Hi,
I would like to start porting acceleration_firmware_ultra96v2 for krs_beta/1.0. Looking at the install instrucctions it states that uses Ubuntu 20.04+vitis 2021.2+Ros2 Rolling
But Ros2 Rolling is a development distro, so it changes over time, so it would be better to use Humble (which has LTS up to May 2027). But, if I use Humble, it states that has binaries for Ubuntu 22.04 (which is also LTS up to April 2027), to use it on Ubuntu 20.04, I should install from sources
Besides that, Vitis is now on 2022.1, so which approach would be better?
a) Use Ubuntu 20.04+vitis 2021.2+Ros2 Humble? (similar to krs_alpha, only ROS2 change, but I need to build ROS2 from sources and there is no assurance about compatibility)
b) Use Ubuntu 20.04+vitis 2021.2+Ros2 Rolling as stated in the install instructions? (But how can I assure that the Ros2 Rolling version used to built the firmware will be the same Ros2 Rolling version at later time?)
c) Use Ubuntu 22.04+vitis 2022.1+Ros2 Humble (which has LTS on ROS and Ubuntu and has the latest release of Vitis, but there is no assurance about compatibility and has a different toolset than krs_alpha)
Any thought/advice?
Regards,
Pedro

Refer to #20 for the methodology.

Hello,

I am trying to add a subproject for the stereo_image_proc accelerated disparity node but I do not see where to add in the subprojects.

should I make a pull request on the image_pipeline repo? The PR would be WIP, but need feedback from community on colcon build errors.

Follows from #19. Summarizing easily measurable dissemination efforts that happened as part of the HAWG:

New projects during 2022

• RobotPerf, RobotPerf provides an open reference benchmarking suite that is used to evaluate robotics computing performance fairly with ROS 2 as its common baseline, so that robotic architects can make informed decisions about the hardware and software components of their robotic systems.
• Robotics MCU: an open source software and hardware ROS 2 microcontroller unit (MCU) powered by RISC-V. The project's goal is to design and develop an open source software and hardware robotics microcontroller unit (Robotics MCU) powered by RISC-V that delivers lower latency and additional real-time capabilities in ROS 2 MCU interactions. The ultimate objective of the project is to design an MCU that contains a native ROS 2 hardware implementation.
• Robotics Processing Unit: a robot-specific processing unit that uses hardware acceleration and maps robotics computations efficiently to its CPUs, FPGAs and GPUs to obtain best performance. In particular, it specializes in improving the Robot Operating System (ROS 2) related robot computational graphs on underlying compute resources.

Tracking progress

Key milestones

Key articles and posts in traceable digital media

Meeting recordings (YouTube channel)

Goals for 2023

The Hardware Acceleration Working Group has grown significantly over 2022. The working group has several key objectives for 2023. The first objective is to develop and publish a comprehensive set of benchmarking tools packed in a suite (RobotPerf) for measuring the performance and efficiency of various software components (ROS packages) and hardware solutions commonly used in robotics. This will enable members of the working group to accurately compare and evaluate the performance of different hardware options and make informed decisions about which components to use in their own projects.

The second objective is to increase the number of vendors participating in the working group. By engaging in targeted outreach and engagement efforts, the group aims to bring more vendors on board, which will provide more options for members and increase the overall diversity of hardware components available for testing and evaluation.

The third objective is to increase the number of collaborations with industry partners. This will gather practical experience and feedback on the performance of hardware acceleration techniques in real-world robotics applications and will also increase the working group's visibility and impact.

The fourth objective is to continue investing resources in the ongoing strategic projects announced during 2022. In particular RobotPerf, Robotics MCU and the Robotics Processing Unit.

Altogether, the objectives for the coming year look as follows:

I would like to use this board to create low cost autonomous vehicles. Need hw acceleration enabled to process visual odometry.

https://m.alibaba.com/product/1600074686709/lichee-tang-HEX-ZYNQ7020-FPGA-Development.html

Hello,

I followed the instructions on https://news.accelerationrobotics.com/ros-2-humble-in-nvidia-xavier-agx-with-yocto/

But unfortunately I got the following error when bitbaking demo-image-ros2:

It seems that one of the ros examples is causing trouble. I will attempt again after removing examples-rclcpp* from the bb description.

Best Regards,
C.A.

can@sidekick:~/tegra-bsp-honister/build$ bitbake demo-image-ros2
Loading cache: 100% |#######################################################################################################################################################################| Time: 0:00:01
Loaded 5185 entries from dependency cache.
NOTE: Resolving any missing task queue dependencies

Build Configuration:
BB_VERSION = "1.52.0"
BUILD_SYS = "x86_64-linux"
NATIVELSBSTRING = "universal"
TARGET_SYS = "aarch64-oe4t-linux"
MACHINE = "jetson-agx-xavier-devkit"
DISTRO = "tegrademo"
DISTRO_VERSION = "3.4.3+snapshot-20230215"
TUNE_FEATURES = "aarch64 armv8a crc"
TARGET_FPU = ""
DISTRO_NAME = "OE4Tegra Demonstration Distro"
ROS_DISTRO = "humble"
ROS_VERSION = "2"
ROS_PYTHON_VERSION = "3"
meta = "HEAD:580532cfd0c23e27a366c074e806fc0b6908b874"
meta-tegra
contrib = "HEAD:b2481c12ae0468c85b76332faa2922682245e185"
meta-oe
meta-python
meta-networking
meta-filesystems = "HEAD:a19d1802b15fe07e9b1e7584ff9af7c33bfe642a"
meta-virtualization = "HEAD:bd7511c53b921c9ce4ba2fdb42778ca194ebc3e8"
meta-tegra-community = "HEAD:4a47d3798404904eec5299306d063a6ec753b158"
meta-tegra-support
meta-demo-ci
meta-tegrademo = "honister:a70a14f6403955d62ca53ba19254efa75d29e6f6"
meta-ros2
meta-ros2-humble
meta-ros-common = "honister-humble:59a615d6e1b30f8576711d7281d1be097b25c33c"

Initialising tasks: 100% |##################################################################################################################################################################| Time: 0:00:12
Sstate summary: Wanted 3808 Local 0 Network 0 Missed 3808 Current 1856 (0% match, 32% complete)
NOTE: Executing Tasks
ERROR: examples-rclcpp-minimal-service-0.15.0-2-r0 do_compile: ExecutionError('/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/temp/run.do_compile.2377923', 1, None, None)
ERROR: Logfile of failure stored in: /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/temp/log.do_compile.2377923
Log data follows:
| DEBUG: Executing shell function do_compile
| NOTE: VERBOSE=1 cmake --build /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/build --target all --
| [1/2] /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot-native/usr/bin/aarch64-oe4t-linux/aarch64-oe4t-linux-g++ -DDEFAULT_RMW_IMPLEMENTATION=rmw_fastrtps_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/example_interfaces -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot-native/usr/lib/python3.9/site-packages/numpy/core/include -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/ament_index_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/libstatistics_collector -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl_interfaces -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/builtin_interfaces -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_runtime_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcutils -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_interface -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_runtime_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_fastrtps_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rmw -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_fastrtps_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_introspection_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_introspection_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl_logging_interface -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl_yaml_param_parser -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/tracetools -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcpputils -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/statistics_msgs -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosgraph_msgs -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/action_msgs -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/unique_identifier_msgs -march=armv8-a+crc -fstack-protector-strong -O2 -D_FORTIFY_SOURCE=2 -Wformat -Wformat-security -Werror=format-security -Wdate-time --sysroot=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot -O2 -pipe -g -feliminate-unused-debug-types -fmacro-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0=/usr/src/debug/examples-rclcpp-minimal-service/0.15.0-2-r0 -fdebug-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0=/usr/src/debug/examples-rclcpp-minimal-service/0.15.0-2-r0 -fdebug-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot= -fdebug-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot-native= -fvisibility-inlines-hidden -march=armv8-a+crc -fstack-protector-strong -O2 -D_FORTIFY_SOURCE=2 -Wformat -Wformat-security -Werror=format-security -Wdate-time --sysroot=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot -Wall -Wextra -Wpedantic -std=gnu++17 -MD -MT CMakeFiles/service_main.dir/main.cpp.o -MF CMakeFiles/service_main.dir/main.cpp.o.d -o CMakeFiles/service_main.dir/main.cpp.o -c /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/git/main.cpp
| FAILED: CMakeFiles/service_main.dir/main.cpp.o
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot-native/usr/bin/aarch64-oe4t-linux/aarch64-oe4t-linux-g++ -DDEFAULT_RMW_IMPLEMENTATION=rmw_fastrtps_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/example_interfaces -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot-native/usr/lib/python3.9/site-packages/numpy/core/include -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/ament_index_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/libstatistics_collector -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl_interfaces -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/builtin_interfaces -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_runtime_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcutils -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_interface -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_runtime_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_fastrtps_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rmw -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_fastrtps_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_introspection_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_introspection_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl_logging_interface -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcl_yaml_param_parser -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/tracetools -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rcpputils -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/statistics_msgs -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosgraph_msgs -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_cpp -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rosidl_typesupport_c -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/action_msgs -I/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/unique_identifier_msgs -march=armv8-a+crc -fstack-protector-strong -O2 -D_FORTIFY_SOURCE=2 -Wformat -Wformat-security -Werror=format-security -Wdate-time --sysroot=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot -O2 -pipe -g -feliminate-unused-debug-types -fmacro-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0=/usr/src/debug/examples-rclcpp-minimal-service/0.15.0-2-r0 -fdebug-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0=/usr/src/debug/examples-rclcpp-minimal-service/0.15.0-2-r0 -fdebug-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot= -fdebug-prefix-map=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot-native= -fvisibility-inlines-hidden -march=armv8-a+crc -fstack-protector-strong -O2 -D_FORTIFY_SOURCE=2 -Wformat -Wformat-security -Werror=format-security -Wdate-time --sysroot=/home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot -Wall -Wextra -Wpedantic -std=gnu++17 -MD -MT CMakeFiles/service_main.dir/main.cpp.o -MF CMakeFiles/service_main.dir/main.cpp.o.d -o CMakeFiles/service_main.dir/main.cpp.o -c /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/git/main.cpp
| In file included from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/service.hpp:36,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/callback_group.hpp:25,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/any_executable.hpp:20,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/memory_strategy.hpp:25,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/memory_strategies.hpp:18,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/executor_options.hpp:20,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/executor.hpp:37,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/executors/multi_threaded_executor.hpp:25,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/executors.hpp:21,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/rclcpp.hpp:155,
| from /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/git/main.cpp:19:
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/any_service_callback.hpp: In instantiation of 'struct rclcpp::detail::can_be_nullptr<void (&)(std::shared_ptr<rmw_request_id_s>, std::shared_ptr<example_interfaces::srv::AddTwoInts_Request_<std::allocator > >, std::shared_ptr<example_interfaces::srv::AddTwoInts_Response_<std::allocator > >), void>':
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/any_service_callback.hpp:109:80: required by substitution of 'template<class CallbackT, typename std::enable_if<rclcpp::detail::can_be_nullptr<CallbackT, void>::value, int>::type > void rclcpp::AnyServiceCallback<example_interfaces::srv::AddTwoInts>::set<CallbackT, >(CallbackT&&) [with CallbackT = void (&)(std::shared_ptr<rmw_request_id_s>, std::shared_ptr<example_interfaces::srv::AddTwoInts_Request_<std::allocator > >, std::shared_ptr<example_interfaces::srv::AddTwoInts_Response_<std::allocator > >); typename std::enable_if<rclcpp::detail::can_be_nullptr<CallbackT, void>::value, int>::type = ]'
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/create_service.hpp:43:3: required from 'typename rclcpp::Service::SharedPtr rclcpp::create_service(std::shared_ptrrclcpp::node_interfaces::NodeBaseInterface, std::shared_ptrrclcpp::node_interfaces::NodeServicesInterface, const string&, CallbackT&&, const rmw_qos_profile_t&, rclcpp::CallbackGroup::SharedPtr) [with ServiceT = example_interfaces::srv::AddTwoInts; CallbackT = void (&)(std::shared_ptr<rmw_request_id_s>, std::shared_ptr<example_interfaces::srv::AddTwoInts_Request_<std::allocator > >, std::shared_ptr<example_interfaces::srv::AddTwoInts_Response_<std::allocator > >); typename rclcpp::Service::SharedPtr = std::shared_ptr<rclcpp::Service<example_interfaces::srv::AddTwoInts> >; std::__cxx11::string = std::cxx11::basic_string; rmw_qos_profile_t = rmw_qos_profile_s; rclcpp::CallbackGroup::SharedPtr = std::shared_ptrrclcpp::CallbackGroup]'
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/node_impl.hpp:147:53: required from 'typename rclcpp::Service::SharedPtr rclcpp::Node::create_service(const string&, CallbackT&&, const rmw_qos_profile_t&, rclcpp::CallbackGroup::SharedPtr) [with ServiceT = example_interfaces::srv::AddTwoInts; CallbackT = void (&)(std::shared_ptr<rmw_request_id_s>, std::shared_ptr<example_interfaces::srv::AddTwoInts_Request<std::allocator > >, std::shared_ptr<example_interfaces::srv::AddTwoInts_Response<std::allocator > >); typename rclcpp::Service::SharedPtr = std::shared_ptr<rclcpp::Service<example_interfaces::srv::AddTwoInts> >; std::cxx11::string = std::cxx11::basic_string; rmw_qos_profile_t = rmw_qos_profile_s; rclcpp::CallbackGroup::SharedPtr = std::shared_ptrrclcpp::CallbackGroup]'
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/git/main.cpp:40:82: required from here
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/any_service_callback.hpp:48:74: error: assignment of read-only location 'std::declval<void (&)(std::shared_ptr<rmw_request_id_s>, std::shared_ptr<example_interfaces::srv::AddTwoInts_Request<std::allocator > >, std::shared_ptr<example_interfaces::srv::AddTwoInts_Response<std::allocator > >)>()'
| decltype(std::declval() == nullptr), decltype(std::declval<T &>() = nullptr)>>
| ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
| /home/can/tegra-bsp-honister/build/tmp/work/armv8a-oe4t-linux/examples-rclcpp-minimal-service/0.15.0-2-r0/recipe-sysroot/usr/include/rclcpp/rclcpp/any_service_callback.hpp:48:74: error: assignment of read-only location 'std::declval<void (&)(std::shared_ptr<rmw_request_id_s>, std::shared_ptr<example_interfaces::srv::AddTwoInts_Request<std::allocator > >, std::shared_ptr<example_interfaces::srv::AddTwoInts_Response<std::allocator > >)>()'
| ninja: build stopped: subcommand failed.
| WARNING: exit code 1 from a shell command.
ERROR: Task (/home/can/tegra-bsp-honister/layers/meta-ros/meta-ros2-humble/generated-recipes/examples/examples-rclcpp-minimal-service_0.15.0-2.bb:do_compile) failed with exit code '1'
NOTE: Tasks Summary: Attempted 11451 tasks of which 5777 didn't need to be rerun and 1 failed.

Summary: 1 task failed:
/home/can/tegra-bsp-honister/layers/meta-ros/meta-ros2-humble/generated-recipes/examples/examples-rclcpp-minimal-service_0.15.0-2.bb:do_compile
Summary: There was 1 ERROR message shown, returning a non-zero exit code.

Hi,
I would like to add the ultra96-v2 board to the list of community supported boards because it's popular, so more people could contribute to the ROS 2 HAWG

regards,
Pedro

Push to a public repository in the organization the firmware artifacts to simplify development flows in a ROS 2-centric manner while maintaining a technology (FPGAs/GPUs) and target (embedded, workstation, data center) agnostic.

• Disclose acceleration_firmware ROS 2 package
• Disclose acceleration_firmware_* ROS 2 packages (one for each board supported)

The road-map from now on is (the order might change between some steps, since not all of them are depended to each other):
- Add LWIP to the current cli-test, with necessary functions filled with dummy functionalities.
- err_t vif_init(struct netif *netif)
- err_t vif_link_output(struct netif *netif, struct pbuf *p)
- err_t vif_output(struct netif *netif, struct pbuf *p, ip_addr_t *ipaddr)
- err_t vif_input(struct netif *netif)
- Add test options to current cli-test interface to manipulate the Lwip initialization settings, and trigger some test stimulus.
- Tie the output and input functions to the MAC (This might require some modifications on MAC)
- Test and debug the system using the current built-in loop-back in the MAC.
- Reroute the i2c interface to the PHY - test first using the current i2c functionality.
- Tie the init function to PHY control.
- Test the network on PHY loop-back. (I assume PHY has loop-back functionality).
- Test the network on Hardware tied to a PC. The tests beyond this point are to be evaluated.

• Move to Humble
• Add latest HAWG recordings and videos
• Record changes in reference hardware platforms

Extend the ROS 2 meta build system to include hardware acceleration capabilities.

Using Matrix as an open network for secure, decentralized communication.

Extend the ROS 2 meta build tools (colcon) to facilitate hardware acceleration development flows.

Follow past surveys in the community. Disclose results afterwards.

Rationale: Hardware acceleration involves creating custom compute architectures to improve the computing performance. In a nutshell, by designing specialized acceleration kernels, one can build custom brains for robots to hasten their response time. This becomes specially feasible when using adaptive computing and FPGAs which according to previous benchmarks, deliver best results in robotics with ROS #20 ¹.

Creating such custom compute architectures involves both hardware and software customization, thereby: Yocto. Though complicated, Yocto in combination with hardware acceleration helps deliver high performance production-grade robotic systems.

Bringing ROS 2 Humble support for Yocto is being contributed at ros/meta-ros#1003. The recipes have been validated with various popular SBCs. Instructions on how to reproduce in the links below. If you find any issues, report it and contribute back.

Image	Board	Description
	AMD KR260	The Kria™ KR260 Robotics Starter Kit is a Kria SOM-based development platform for robotics and factory automation applications. With native ROS 2 Humble support, it enables roboticists with a ROS 2-centric dev. flow.
	AMD KV260	The Kria™ KV260 starter kit is a development platform for the K26, the first adaptive Single Board Computer. KV260 offers a compact board for edge vision and robotics applications.
	AMD ZCU102	The ZCU102 Evaluation Kit enables designers to jumpstart designs for automotive, industrial, video, and communications applications. This kit features a Zynq® UltraScale+™ MPSoC with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5F real-time processors, and a Mali™-400 MP2 graphics processing unit.
	AMD ZCU104	The ZCU104 Evaluation Kit enables designers to jumpstart designs for embedded vision applications such as surveillance, Advanced Driver Assisted Systems (ADAS), machine vision, Augmented Reality (AR), drones and medical imaging. This kit features a Zynq® UltraScale+™ MPSoC EV device with video codec and supports many common peripherals and interfaces for embedded vision use case.
	NVIDIA Jetson Nano	The Jetson Nano™ Developer Kit is a small, powerful computer that lets you run multiple neural networks in parallel for applications like image classification, object detection, segmentation, and speech processing. All in an easy-to-use platform that runs in as little as 5 watts.
	Jetson AGX Xavier	The NVIDIA Jetson AGX Xavier Developer Kit is an AI computer for autonomous machines, delivering the performance of a GPU workstation in an embedded module under 30W. Jetson AGX Xavier is designed for robots, drones and other autonomous machines.
	Microchip PolarFire Icicle Kit	The PolarFire SoC Icicle kit is a low-cost development platform that enables evaluation of the five-core Linux capable RISC-V microprocessor subsystem, innovative Linux, and real-time execution, low-power capabilities and the rich set of peripherals of the PolarFire SoC FPGA.

Produce demonstrators with robot components, real robots and fleets that include acceleration to meet their targets.

The ROS 2 Hardware Acceleration Stack is a series of extensions to ROS 2 which allow to leverage hardware acceleration and create custom compute architectures providing a faster ROS 2 execution and a timing-safe event-driven programming interface. The stack is composed of 4 key elements and aims to be hardware and vendor-agnostic:

The ROS 2 Hardware Acceleration Working Group contributes and maintains open source implementations of various components of the stack above. A complete implementation of the ROS 2 Hardware Acceleration Stack including professional support, documentation, examples as well as reference designs is available at Acceleration Robotics' ROBOTCORE™. Other solutions that implement part of the stack include AMD's KRS (the Kria Robotics Stack), or NVIDIA's NITROS (NVIDIA Isaac Transport for ROS).