I have an issue with building the boom-template verisim project, the make process fails and doesn't generate the binary target. I am new to this problem so perhaps I am just doing something wrong. It should be noted the VTestHarness.mk that I think its trying to use is empty in my directory generated-src/boom.system.TestHarness.BoomConfig/VTestHarness.mk
user@syl:~/src/boom-template/verisim$ make
mkdir -p /home/user/src/boom-template/verisim/generated-src
cd /home/user/src/boom-template && java -Xmx2G -Xss8M -jar /home/user/src/boom-template/rocket-chip/sbt-launch.jar ++2.12.4 "runMain boom.system.Generator /home/user/src/boom-template/verisim/generated-src boom.system TestHarness boom.system BoomConfig"
[info] Loading project definition from /home/user/src/boom-template/project
[info] Loading settings from build.sbt ...
[info] Loading settings from build.sbt ...
[info] Loading settings from plugins.sbt ...
[info] Loading project definition from /home/user/src/boom-template/rocket-chip/project
[info] Loading settings from build.sbt ...
[info] Loading settings from build.sbt ...
[info] Loading settings from build.sbt ...
Using addons:
[info] Set current project to boom-template (in build file:/home/user/src/boom-template/)
[info] Set current project to boom (in build file:/home/user/src/boom-template/)
[info] Setting Scala version to 2.12.4 on 8 projects.
[info] Reapplying settings...
Using addons:
[info] Set current project to boom (in build file:/home/user/src/boom-template/)
[info] Set current project to boom (in build file:/home/user/src/boom-template/)
[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list
[info] Running boom.system.Generator /home/user/src/boom-template/verisim/generated-src boom.system TestHarness boom.system BoomConfig
[info] [0.001] Elaborating design...
Building TestHarness for an ExampleBoomSystem.
Interrupt map (2 harts 2 interrupts):
[1, 2] => dut
==Dense BTB==
Sets : 512
Banks : 2
Ways : 4
Branch Levels : 2
Tag Size : 13
Offset Size : 13
==BIM==
(16 Kbits = 2 kB) Bimodal Table (1024 entries across 2 banks)
==TAGE==
4.501953125 kB TAGE Predictor (36 Kbits) (max history length: 90 bits)
TageTable[0] - 1024 entries, 27 bits of history, 9-bit tags, 3-bit counters
TageTable[1] - 1024 entries, 45 bits of history, 9-bit tags, 3-bit counters
TageTable[2] - 1024 entries, 63 bits of history, 9-bit tags, 3-bit counters
TageTable[3] - 1024 entries, 90 bits of history, 9-bit tags, 3-bit counters
==L1-ICache==
Fetch bytes : 16
Block bytes : 64
Row bytes : 16
Word bits : 128
Sets : 64
Ways : 8
Refill cycles : 4
RAMs : (64 x 256) using 2 banks
Dual-banked
I-TLB entries : 32
~*** Two-wide Machine ***~
-== Quad Issue ==-
ExeUnit--
- Mem
ExeUnit--
- ALU
- Mul
- Div
- IFPU
ExeUnit--
- ALU
()
ExeUnit--
- FPU (Latency: 4)
- FDiv/FSqrt
- FPIU (writes to Integer RF)
==ROB==
Machine Width : 2
Rob Entries : 80
Rob Rows : 40
Rob Row size : 6
log2Ceil(width): 1
FPU FFlag Ports: 2
FPU Unit Enabled
VM Enabled
FDivSqrt Enabled
Fetch Width : 8
Decode Width : 2
Issue Width : 4
ROB Size : 80
Issue Window Size : List(20, 20, 20) (Age-based Priority)
Load/Store Unit Size : 32/18
Num Int Phys Registers: 100
Num FP Phys Registers: 64
Max Branch Count : 8
BTB Size : 2048 entries (512 x 4 ways)
RAS Size : 8
Rename Stage Latency : 2
RegRead Stage Latency : 1
==Integer Regfile==
Num RF Read Ports : 6
Num RF Write Ports : 3
RF Cost (R+W)*(R+2W) : 108
Bypassable Units : List(true, true, true)
Num Slow Wakeup Ports : 2
Num Fast Wakeup Ports : 2
Num Bypass Ports : 4
==Floating Point Regfile==
Num RF Read Ports : 3
Num RF Write Ports : 2
RF Cost (R+W)*(R+2W) : 35
Bypassable Units : List(false, false)
Num Wakeup Ports : 2
Num Bypass Ports : 0
DCache Ways : 8
DCache Sets : 64
ICache Ways : 8
ICache Sets : 64
D-TLB Entries : 16
I-TLB Entries : 32
Paddr Bits : 32
Vaddr Bits : 39
<stdout>: Warning (simple_bus_reg): Node /soc/external-interrupts missing or empty reg/ranges property
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-unknown";
L13: cpus {
#address-cells = <1>;
#size-cells = <0>;
L5: cpu@0 {
clock-frequency = <0>;
compatible = "ucb-bar,boom0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <16>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L7>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L7: memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
L12: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L2: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L3 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L10: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
reg-names = "mem";
};
L6: external-interrupts {
interrupt-parent = <&L0>;
interrupts = <1 2>;
};
L0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L3 11 &L3 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <3>;
riscv,ndev = <2>;
};
L8: mmio-port-axi4@60000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x60000000 0x20000000>;
};
L9: rom@10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x10000>;
reg-names = "mem";
};
};
};
Generated Address Map
0 - 1000 ARWX debug-controller@0
3000 - 4000 ARWX error-device@3000
10000 - 20000 R XC rom@10000
2000000 - 2010000 ARW clint@2000000
c000000 - 10000000 ARW interrupt-controller@c000000
60000000 - 80000000 RWX mmio-port-axi4@60000000
80000000 - 90000000 RWXC memory@80000000
[info] [54.599] Done elaborating.
[success] Total time: 62 s, completed Mar 19, 2019, 4:50:46 PM
java -Xmx2G -Xss8M -cp "/home/user/src/boom-template/rocket-chip/firrtl/utils/bin/firrtl.jar":""/home/user/src/boom-template/rocket-chip/target/scala-2.12/classes:/home/user/src/boom-template/rocket-chip/chisel3/target/scala-2.12/*"" firrtl.Driver -i /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig.fir -o /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig.v -X verilog -faf /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig.anno.json
Default case invoked for:
opcode = 0, "Node"
Default case invoked for:
opcode = 0, "Node"
Default case invoked for:
opcode = 0, "Node"
Default case invoked for:
opcode = 0, "Node"
Default case invoked for:
opcode = 0, "Node"
Total FIRRTL Compile Time: 185435.4 ms
rm -rf /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig
mkdir -p /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig
/home/user/src/boom-template/verisim/verilator/install/bin/verilator --cc --exe --top-module TestHarness +define+PRINTF_COND=\$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) +define+STOP_COND=\$c\(\"done_reset\"\) --assert --output-split 20000 --no-threads -Wno-STMTDLY -Wno-CMPCONST --x-assign unique -I/home/user/src/boom-template/testchipip/vsrc -I/home/user/src/boom-template/rocket-chip/src/main/resources/vsrc -O3 -CFLAGS " -O1 -std=c++11 -I/opt/riscv/include -D__STDC_FORMAT_MACROS -DVERILATOR -DTEST_HARNESS=VTestHarness -include /home/user/src/boom-template/rocket-chip/src/main/resources/csrc/verilator.h -include /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig.plusArgs" -Mdir /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig \
-o /home/user/src/boom-template/verisim/simulator-boom.system-BoomConfig /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig.v /home/user/src/boom-template/rocket-chip/src/main/resources/csrc/SimDTM.cc /home/user/src/boom-template/rocket-chip/src/main/resources/csrc/SimJTAG.cc /home/user/src/boom-template/rocket-chip/src/main/resources/csrc/remote_bitbang.cc /home/user/src/boom-template/rocket-chip/src/main/resources/csrc/emulator.cc -LDFLAGS " -L/opt/riscv/lib -Wl,-rpath,/opt/riscv/lib -L/home/user/src/boom-template/verisim -lfesvr -lpthread" \
-CFLAGS "-I/home/user/src/boom-template/verisim/generated-src -include /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig/VTestHarness.h"
touch /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig/VTestHarness.mk
make VM_PARALLEL_BUILDS=1 -C /home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig -f VTestHarness.mk
make[1]: Entering directory '/home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig'
make[1]: *** No targets. Stop.
make[1]: Leaving directory '/home/user/src/boom-template/verisim/generated-src/boom.system.TestHarness.BoomConfig'
Makefile:90: recipe for target '/home/user/src/boom-template/verisim/simulator-boom.system-BoomConfig' failed
make: *** [/home/user/src/boom-template/verisim/simulator-boom.system-BoomConfig] Error 2
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