pyhdl20 / openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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Table of contents

• Overview
• Prerequisites
• Getting Started - Directory Setup
• Getting Started - OpenLANE Flow Setup
• Getting Started - PDK Setup
  • Setting up skywater-pdk
  • Setting up other PDKs
• Getting Started - How to Run
  • Running the flow
  • Command line arguments
  • Adding a design
• The Flow
  • Stages
  • Flow output
  • Flow configuration
  • Interactive Mode
• Regression And Design Configurations Exploration

Overview

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII - this capability will be released in the coming weeks with completed SoC design examples that have been sent to SkyWater for fabricaiton.

Prerequisites

• Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice
• Magic VLSI Layout Tool is needed to run open_pdks -- version >= 8.3.25

For more details about the docker container and its process, the following instructions walk you through the process of using docker containers to build the needed tools then integrate them into OpenLANE flow.

Setting up the PDK: skywater-pdk

• Clone and build one skywwater-pdk variant(s) inside the pdks directory:

  • To setup one variant only

      export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>
  cd  $PDK_ROOT
      git clone [email protected]:google/skywater-pdk.git
      cd skywater-pdk
      git checkout 4e5e318e0cc578090e1ae7d6f2cb1ec99f363120
      git submodule update --init libraries/sky130_fd_sc_hd/latest
      make sky130_fd_sc_hd 

  • To setup other variants:
    • replace sky130_fd_sc_hd with any of the following list:
      • sky130_fd_sc_hs
      • sky130_fd_sc_ms
      • sky130_fd_sc_ls
      • sky130_fd_sc_hdll

• Setup the configurations and tech files for Magic, Netgen, OpenLANE using open_pdks:

      cd $PDK_ROOT
  git clone [email protected]:efabless/open_pdks.git -b rc2
      cd open_pdks
      make
      make install-local

• To set the PDK_VARIANT (the default value is set to sky130_fd_sc_hd)

  • Open configuration/general.tcl

  • set PDK_VARIANT to one of the following:

      - sky130_fd_sc_hs
      - sky130_fd_sc_ms
      - sky130_fd_sc_ls
      - sky130_fd_sc_hdll
    

Refer to this for more details on the structure.

Setting up OpenLANE

    git clone [email protected]:efabless/openlane --branch rc2
    cd openlane/docker_build
    make merge
    cd ..

Running OpenLANE

Issue the following command to open the docker container from path/to/openlane to ensure that the output files persist after exiting the container:

   docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc2

Note: this will mount the openlane directory inside the container.

Use the following example to check the overall setup:

./flow.tcl -design spm

To run OpenLANE on multiple designs at the same time, check this section.

Command line arguments

The following are arguments that can be passed to flow.tcl

Argument	Description
-design (Required)	Specifies the design folder. A design folder should contain a config.tcl definig the design parameters. If the folder is not found, ./designs directory is searched
-config <name> (Optional)	Specifies the design's configuration file for while running the flow. For example, to run the flow using designs/spm/config2.tcl Use run ./flow.tcl -design spm -config config2.tcl By default config.tcl is used.
-tag <name> (Optional)	Specifies a name for a specific run. If the tag is not specified, a timestamp is generated for identification of that run. Can Specify the configuration file name in case of using -init_design_config
-run_path <path> (Optional)	Specifies a path to save the run in. By default the run is in design_path/, where the design path is the one passed to -design
-save (Optional)	A flag to save a runs results like .mag and .lef in the design's folder
-save_path <path> (Optional)	Specifies a different path to save the design's result. This options is to be used with the -save flag
-init_design_config (Optional)	Creates a tcl configuration file for a design. -tag <name> can be added to rename the config file to <name>.tcl
-overwrite (Optional)	Flag to overwirte an existing run with the same tag
-interactive (Optional)	Flag to run openlane flow in interactive mode
-file <file_path> (Optional)	Passes a script of interactive commands in interactive mode

Adding a design

To add a new design, follow the instructions provided here

This file also includes useful information about the design configuration files. It also includes useful utilities for exploring and updating design configurations for each (PDK,PDK_VARIANT) pair.

OpenLANE Architecture

OpenLANE Design Stages

OpenLANE flow consists of several stages. By default all flow steps are run in sequence. Each stage may consist of multiple sub-stages. OpenLANE can also be run interactively which will be shown below.

1. Synthesis
   1. yosys - Performs RTL synthesis
   2. abc - Performs technology mapping
   3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
2. Floorplan and PDN
   1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
   2. ioplacer - Places the macro input and output ports
   3. pdn - Generates the power distribution network
   4. tapcell - Inserts welltap and decap cells in the floorplan
3. Placement
   1. RePLace - Performs global placement
   2. Resizer - Performs optional optimizations on the design
   3. OpenDP - Perfroms detailed placement to legalize the globally placed components
4. CTS
   1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
5. Routing *
   1. FastRoute - Performs global routing to generate a guide file for the detailed router
   2. TritonRoute - Performs detailed routing
6. GDSII Generation
   1. Magic - Streams out the final GDSII layout file from the routed def
7. Checks
   1. Magic - Performs DRC Checks & Antenna Checks
   2. Netgen - Performs LVS Checks

OpenLANE integrated several key open source tools over the execution stages:

• RTL Synthesis, Technology Mapping, and Formal Verification : yosys + abc
• Static Timing Analysis: OpenSTA
• Floor Planning: init_fp, ioPlacer, pdn and tapcell
• Placement: RePLace (Global), Resizer (Optimizations), and OpenDP (Detailed)
• Clock Tree Synthesis: OpenROAD/TritonCTS
• Fill Insertion: OpenROAD/filler_placement
• Routing: FastRoute (Global) and TritonRoute (Detailed)
• GDSII Streaming out: Magic
• DRC Checks: Magic
• LVS check: Netgen
• Antenna Checks: Magic

OpenLANE Output

All output run data is placed by default under ./designs/design_name/runs. Each flow cycle will output timestamp-marked foler containing the following file structure:

designs/<design_name>
├── config.tcl
├── runs
│   ├── <tag>
│   │   ├── config.tcl
│   │   ├── logs
│   │   │   ├── cts
│   │   │   ├── floorplan
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── reports
│   │   │   ├── cts
│   │   │   ├── floorplan
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── results
│   │   │   ├── cts
│   │   │   ├── floorplan
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   └── tmp
│   │       ├── cts
│   │       ├── floorplan
│   │       ├── magic
│   │       ├── placement
│   │       ├── routing
│   │       └── synthesis

Flow configuration

1. PDK / technology specific
2. Flow specific
3. Design specific

• A PDK should define at least one variant for the PDK. A common configuration file for all PDK variants is located in:

  $PDK_ROOT/$PDK/config.tcl
  

  • Sometimes the PDK comes with several Standard Cell Libraries or Metal Stacks. Each is considered as a PDK variant. A variant configuration file defines extra variables specific to the variant. It may also override variables in the common PDK configuration file which is located in:

    $PDK_ROOT/$PDK/$PDK_VARIANT/config.tcl
    

  • More on configuring a new PDK in this section

• Flow specific variables are related to the flow and are initialized with default values in:

  ./configuration/
  

• Finally, each design should have it's own configuration file with some required variables which are available in this list. A design configuration file may override any of the variables defined in PDK or flow configuration files. This is the global configurations for the design:

  ./designs/<design>/config.tcl
  

  • More on design configurations in here

A list of all available variables can be found here.

Interactive Mode

You may run the flow interactively by using the -interactive option:

./flow.tcl -interactive

A tcl shell will be opened where the openlane package is automatically sourced:

% package require openlane 0.9

Then, you should be able to run the following commands:

0. Any tcl command.
1. prep -design <design> -tag <tag> -config <config> -init_design_config -overwrite similar to the command line arguments, design is required and the rest is optional
2. run_synthesis
3. run_floorplan
4. run_placement
5. run_cts
6. run_routing
7. run_magic
8. run_magic_spice_export
9. run_magic_drc
10. run_netgen
11. run_magic_antenna_check

The above commands can also be written in a file and passed to flow.tcl:

./flow.tcl -interactive -file <file>

Note 1: Currently, configuration variables have higher priority over the above commands so if RUN_MAGIC is 0, command run_magic will have no effect.

Note 2: Currently, all these commands must be run in sequence and none should be omitted.

Regression And Design Configurations Exploration

As mentioned earlier, everytime a new design or a new (PDK,PDK_VARIANT) pair is added, or any update happens in the flow tools, a re-configuration for the designs is needed. The reconfiguration is methodical and so an exploration script was developed to aid the designer in reconfiguring his designs if needed. As explained here that each design has multiple configuration files for each (PDK,PDK_VARIANT) pair.

Overview

OpenLANE provides run_designs.py, a script that can do multiple runs in a parallel using different configurations. A run consists of a set of designs and a configuration file that contains the configuration values. It is useful to explore the design implementation using different configurations to figure out the best one(s).

Also, it can be used for testing the flow by running the flow against several designs using their best configurations. For example the following run: spm using its default configuration files config.tcl. :

python3 run_designs.py --designs spm xtea md5 aes256 --tag test --threads 3

For more information on how to run this script, refer to this file

For more information on design configurations, how to update them, and the need for an exploration for each design, refer to this file