openmri / ocra

MRI console

OCRA: The Open Source Console for Realtime Acquisitions

General

This repository contains the seedlings for your very own MRI system. This is all this is, just a seedling. Okay, its a little more, it also contains a tool for controlling AC/DC shim coils.

Seriously though, this repository is mostly code generated back in 2017 to demonstrate that an MRI machine can be built using just a Red Pitaya as control electronics, significantly lowering the entrance threshold for researchers and hobbyists alike. We are trying to provide code to make this more than that as time allows. Certainly, if you like, your input on any aspect of this project is more than welcome!

If you're interested in learning more about getting started with OCRA, check out The OCRA github page.

We also have a blog page about some of the hardware at the The OCRA blog

Its not straight-forward to build the FPGA bitfiles, at least until we provide better documentation. Until then, please find the bitfiles for the tabletop OCRA MRI setups here: Downloadable binaries

How to update Relax 2.0 on your OCRA Tabletop MRI System (RP125-14, RPi 3B+)

Make a backup of the rawdata, imagedata and protocol folder if necessary.

Remove the old relax2 folder completely and replace it with the newest relax2 folder from github.

Remote access the Red Pitaya via ssh and stop the running server.

Copy the relax_server_dev.c file from the updated relax2/server folder to the Red Pitaya, compile it and restart the server afterwards.

More detailed instructions can be found in the relax2/server/README.txt (chapter 1 and 2).

ocra's Issues

Build an ARISE demo setup

Build an application to demonstrate ARISE.

Build a digital version of DOI: 10.1002/mrm.21702

An unnecesary log

All the print have one useless "%d" here

printf("Set gradient offsets to 0 0 0 %d\n");

should be fixed to

printf("Set gradient offsets to 0 0 0 %d\n");

Remove CIC compensation filter from FPGA to deal with unnecessary data delay

Create a UART core for custom serial interfaces routed via the PL

For in-scanner-room applications of Zynq FPGAs, a fiberoptic communications link can be desirable. Implement a basic UART core that can operate a fiber-optic connection via PL GPIO pins and look like a UART to the PS.

Provide full integration with the PS software.

A question about the how to compute pulse width

Hello,

From this line I can see 32 points (64/2 for complex numbers) will get a pulse width of 50us (the lead-in).

But if I pass 60 as duration, from oscilloscope I can get a pulse almost 50us.

I also noticed that tx_devider will affect the width of pulse.

I need to control as prcise as possible for pulse width, so how to compute an precise pulse width here ?

Implement IP core for control of ADS8168

Add some basic documentation on how to build etc.

Change the attenuator address

The attenuator uses the address 000 at the moment. This will cause resets sometimes due to SPI bus coupling. When receiving just zeros as data the 000 attenuator reacts when a spike triggers the letch line. The attenuator will set itself to -31.75dB and "no" TX puls will get through. A address like 101 will most likely avoid this. Also a further implementation can allow for communication with more than one attenuator.

The address is set in the server somewhere.

snickerdoodle-black missing pins

The advertisement says there should be 167 GPIO pins, but our pins file has only 5x25 = 125. Where are the others?

Setup binary validation

Add a target to the Makefile to generate a text file with the md5sums of all the deliverable files
Add a script validate_binaries that will check the files on the redpitaya to make sure their md5sums match

Write a documentation on how to configure networking on the ocra setups

Write a nice manual about the various combinations network can be setup on the stemlab boards, with details on how to do the configurations.

Setup Makefile and Ports to support multiple boards

Make sure the Makefile does

• check that the selected board is a valid and supported board
• the project being built is available for this board
• select the right PART from the board selected

Make sure the projects and board designs

• specify which boards they support
• include the correct constraints

Make some examples:

• blinkenlights should be supported for each board

Make the input channel on the Red Pitaya selectable

Add a feature to the block design to make the input channel on the red pitaya selectable.
Add function to the ocra-server to control it

How to change the dwell_time and acqusion_points during acquisition period?

Dear All,

How to change the dwell_time and acqusion_points during acquisition period?
For example, in the mri_lab_rt.c, 5000*10 samples was transfer. Is is possible to only transfer 2048 data points?

BW

Put Relax2 into a proper poetry project

Right now Relax2 is "naked". Create a proper poetry project to clean it up, and make it testable.

Who wrote the FPGA code and is there any detailed documentation for it?

Hello, I read the OCRA thesis but i could not figure out where is the FPGA code coming from, nor if there is a documentation for the code. could you please provide details on that as it would be helpful.

unreachable code

flipangleDialog.py line 74
Code:
except IOError as e:
print("\tError: required txt file doesn't exist.")
return
print("\tUploaded successfully to server.") <-- unreachable should be above

Update scripts to create platforms

In order to make full use of Vitis' platform concept, update our scripts to generate proper platform projects.

Port to Vitis 2022.2

Build a mock ocra-server

Build a simple mock ocra-server to allow for integration testing.

Build a sync interface to Siemens 10MHz clock

Build an interface that allows synchronization to the Siemens 10MHz clock

uninitialized variable

Applications/shim_controller/shim_controller_test.c line 230
Code:
void *cfg, *sts;
vs
rx_cntr = ((uint16_t *)(sts + 0));

Build a continuous ASL labelling setup

Build an application for cASL labelling

More Makefile cleanups

Trim everything unneeded out of the Makefile, fix all the rules, so the builds can continue from where they left off, etc.

Add board support files for Vitis

In order to make full use of platform projects and fsbl generation, it would be helpful to provide the board files for the boards involved in this project.

• Provide some documentation on how to install them
• In the documentation also link to the original sources, for cases where these board files exist already

Enable second UART for snickerdoodle

Make sure UART1 is configured correctly for the snickerdoodle-black

Implement proper RX data packetization