Comments (1)
Hello,
thank you for your interest. Most of the HDL code was written by me with some borrowed code from other projects. Everything is inside the HDL folder of this repository. We have not bothered with any detailed documentation as of yet.
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Related Issues (20)
- More Makefile cleanups
- Setup Makefile and Ports to support multiple boards
- Put Relax2 into a proper poetry project
- Make the input channel on the Red Pitaya selectable
- Build a mock ocra-server
- Build an ARISE demo setup
- Build a continuous ASL labelling setup
- Build a sync interface to Siemens 10MHz clock HOT 1
- Write a documentation on how to configure networking on the ocra setups
- Change the attenuator address
- Add board support files for Vitis
- Update scripts to create platforms
- snickerdoodle-black missing pins HOT 1
- Create a UART core for custom serial interfaces routed via the PL
- Implement IP core for control of ADS8168
- Setup binary validation
- uninitialized variable HOT 3
- Enable second UART for snickerdoodle
- unreachable code
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