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View Code? Open in Web Editor NEWImplementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
Hi Omarelhedaby,
Thanks for your great work! Benifit a lot from your work & code.
While studying your code, I found something strange in the reciprocal module(floatReciprocal.v). When input is 1(32'h3F800000), output is to be 1 for granted. But the real output is 0.5. I debug this problem and I found it is caused by not considering the carry bit in floatadd module. The exponent of the output in reciprocal module is 8'b11111101-number[30:23], this is where the problem exists.
Considering the impact of carry-bit, I try to rewrite the expression of exponent as 8'b01111110-number[30:23] + mux[30:23]. It works, but one more adder used. This case rarely occurs, but I think it is better to be noted.
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