olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

FuseSoC

Introduction

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code.

Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

FuseSoC makes it easier to

• reuse existing cores
• create compile-time or run-time configurations
• run regression tests against multiple simulators
• port designs to new targets
• let other projects use your code
• set up continuous integration

To learn more about FuseSoC head over to the User Guide.

Getting started

Installing the latest release

FuseSoC works on Linux, Windows, and macOS. It is written in Python and can be installed like any other Python package through "pip". Please refer to the full list of system requirements and installation instructions in the Installation section in the User Guide.

Quick start

To check if FuseSoC is working, and to get an initial feeling for how FuseSoC works, you can try to simulate a simple hardware design from our core libray.

First, create and enter an empty workspace

mkdir workspace
cd workspace

Install the FuseSoc base library into the workspace

fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores

Get a list of cores found in the workspace

fusesoc core list

If you have any of the supported simulators installed, you can try to run a simulation on one of the cores as well. For example, fusesoc run --target=sim i2c will run a regression test on the core i2c with Icarus Verilog. If you want to try another simulator instead, add e.g. --tool=modelsim or --tool=xcelium between run and i2c.

fusesoc --help will give you more information on commands and switches.

Did it work? Great! FuseSoC can be used to create FPGA images, perform linting, manage your IP libraries or do formal verification as well. Check out the online documentation documentation to learn more about creating your own core files and using existing ones. If it didn't work, please get in touch (see below).

Next steps

A good way to get your first hands-on experience with FuseSoC is to contribute to the LED to Believe project. This project aims to used FuseSoC to blink a LED on every available FPGA development board in existence. There are already around 40 different boards supported. If your board is already supported, great, then you can run your first FuseSoC-based design. If it's not supported, great, you now have the chance to add it to the list of supported boards. Either way, head over to LED to Believe to learn more and see how to go from a blinking LED to running a RISC-V core on an FPGA.

Need help?

FuseSoC comes with extensive online documentation.

For quick communication with the active developers, feel free to join us at the FuseSoC chat.

If you have found an issue, or want to know more about currently known problems, check out the issue tracker on GitHub.

If you are looking for professional paid support, we are happy to provide feature additions, bug fixes, user training, setting up core libraries, migrating existing designs to FuseSoC and other things. Please contact [email protected] for more information.

Contributing to FuseSoC

FuseSoC is developed by an active and friendly community, and you're welcome to join! You can read more about setting up a development environment in our Developer's Guide.

You can file bug reports and propose changes in the olofk/fusesoc repository on GitHub.

Further reading

• A Scalable Approach to IP Management with FuseSoC paper and slides from OSDA 2019
• Antmicro blog post on how to use FuseSoC as a linter
• FuseSoC-related posts on the Tales from Beyond the Register Map blog
• Presentation from RISC-V Week 2022
• Presentation from Latch-Up Portland 2019
• Presentation from WOSH 2019
• Presentation from ORConf 2017
• Presentation from ORConf 2016

License

FuseSoC is licensed under the permissive 2-clause BSD license, freely allowing use, modification, and distribution of FuseSoC for all kinds of projects. Please refer to the LICENSE file for details.

fusesoc's Issues

Fusesoc for Actel ProASIC3

What changes needed to use this for an Actel ProASIC3? Which modules need customization?

simulation problem

Hi,
when i try to do a simple simulation by calling
fusesoc sim --sim modelsim wb_sdram_ctrl

I get the the following error:
File "build/bdist.linux-x86_64/egg/fusesoc/simulator/modelsim.py", line 24, in configure
File "build/bdist.linux-x86_64/egg/fusesoc/simulator/simulator.py", line 67, in configure
File "build/bdist.linux-x86_64/egg/fusesoc/edatool.py", line 100, in parse_args
KeyError: 'elf_load'

I have tried also using other cores and also icarus simulator but I always get the same error.

Any idea?

Pale coloured font on white background console unreadable

I use a console with a white background and find it very hard to read the output of fusesoc. I am also echoing the comments of some users who used fusesoc at chiphack. Is it possible to use the default font colour of the terminal instead, and perhaps print certain headings in brighter colours, as needed?

Special backend: vivado-yosys

It would be great to launch a variant where the synthesis is done by yosys and only the implementation by vivado. If I understand it correctly, Yosys can:

• Compile to EDIF or RTL Verilog with instantiated Xilinx primitives for 7-Series FPGA
• Compile to EDIF or RTL Verilog for others

Plot the dependency graph with graphviz

The idea is to plot a dependency graph for the given core/system

Cannot compile simulate de0_nano using Icarus?

Do I have to use modelsim for de0_nano simulation?

command:
~/sim$ fusesoc sim de0_nano --vcd --timeout=100000 --bootrom_file=spi_uimage_loader.vh

Output:

WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_altera_ddr_wrapper
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in stream_utils-1.0
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in vlog_tb_utils
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in elf-loader
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_sdram_ctrl
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ram_wb
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in fifo-1.0
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon
WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon-1.0
INFO: Preparing elf-loader
INFO: Preparing jtag_vpi-r2
INFO: Preparing mt48lc16m16a2
INFO: Preparing s25fl064p-1.7
INFO: Preparing vlog_tb_utils-1.0
INFO: Preparing adv_debug_sys
INFO: Preparing altera_virtual_jtag
INFO: Preparing gpio
INFO: Preparing i2c-1.13
INFO: Preparing jtag_tap-1.13
INFO: Preparing mor1kx-3.1
INFO: Preparing or1k_bootloaders-0.9
INFO: Preparing simple_spi-1.6
INFO: Preparing uart16550-1.5.4
INFO: Preparing wb_bfm-1.0
INFO: Preparing verilog-arbiter-r1
INFO: Preparing verilog_utils
INFO: Preparing wb_common
INFO: Preparing wb_intercon-1.0
INFO: Preparing wb_ram-1.0
INFO: Preparing wb_sdram_ctrl-r2
INFO: Preparing wiredelay
INFO: Preparing de0_nano

INFO: Running /home/esc/.local/share/orpsoc-cores/cores/elf-loader/check_libelf.sh
INFO: Running /home/esc/.local/share/orpsoc-cores/systems/de0_nano/legacy_symlink.sh
/home/esc/Desktop/csaw_esc_2016/sim/build/de0_nano/src/de0_nano
/home/esc/Desktop/csaw_esc_2016/sim/build/de0_nano/src/de0_nano_0
Compiling /home/esc/Desktop/csaw_esc_2016/sim/build/de0_nano/src/elf-loader/elf-loader.c...
Compiling /home/esc/Desktop/csaw_esc_2016/sim/build/de0_nano/src/elf-loader/vpi_wrapper.c...
Making elf-loader.vpi from elf-loader.o vpi_wrapper.o...
Compiling /home/esc/Desktop/csaw_esc_2016/sim/build/de0_nano/src/jtag_vpi-r2/jtag_vpi.c...
Making jtag_vpi-r2.vpi from jtag_vpi.o...
iverilog: invalid option -- 'P'
ERROR: Failed to build simulation model
ERROR: Failed to compile Icarus Simulation model

simulation problem with questasim (modelsim)

Hi,

when I am using icarus as the simulator everythin is fine but when I try it with questasim (--sim=modelsim) which has the same interface and commands as modelsim I got the following error:

Running: .../check_libelf.sh
ld: cannot find -lelf
ERROR: Failed to build simulation model
ERROR: Linking of elf-loader failed

However, the libelf-dev package is already installed and the MODEL_TECH evn. variable is set.

Trouble adding a new peripheral to the system

Dear Olof,
I had been able to setup or1200-generic, and compile and run a simple c program to print "Hello World" using the system.Now i need to add a computational peripheral to the system and run an application which uses the new peripheral.
Are there any readme or tutorials on how to add peripheral to the system?. I have wrapped the peripheral to make it wishbone compliant.

Thanks in advance
Jeebu

Handle different SoCs with different boards

Hi,

I was wondering if there is a plan to add the concept of a board. With the OpenRISC background, currently a system is more or less a board. I plan to have a different SoC now and have as much reuse as possible.

Here is what I am doing now:

• A core <SoC> for the SoC toplevel that has a "generic" interface
• A core <Board> that contains the board-specific blocks, like the DDR controller etc.
• Create a system: <SoC>-<Board> that has a glue logic toplevel

I think it will be complex to find a really generic way.

Best,
Stefan

Enable use of different files depending on build environment

We're currently trying to get a Xilinx DRAM controller (MIG) to work. In the core file, we include the IP-XACT file (*.xci), which then causes Vivado to generate the code for this IP. Right now, it looks like that:

[fileset core]
usage = vivado
files =
  ip/mig_7series.xci[file_type=xci]
  ip/mig_config.prj[file_type=data]

Unfortunately, (almost) each Vivado version comes with a new version of the MIG core. Xilinx provides a upgrade_ip TCL command to upgrade between the different cores. That works well as long as the core API does not change. So using a old version of the core and then upgrading it might work for many use cases.

When the core API changes, this does not work. In these cases, we need to include different source files depending on the used Vivado version: a different xci, prj and verilog file which wraps the core.

What would be the right way to support such a feature? I propose to have "conditional filesets", e.g. like this:

[fileset core_mig_3.x]
usage = vivado
onlyif = $vivado_version == 2016.2 || $vivado_version == 2016.1
files =
  rtl/verilog/mig_wrapper.v
  ip/mig_7series.xci[file_type=xci]
  ip/mig_config.prj[file_type=data]


[fileset core_mig_2.x]
usage = vivado
onlyif = $vivado_version == 2015.1 or $vivado_version == 2015.2
files =
  rtl/verilog/mig_wrapper.v
  ip/mig_7series.xci[file_type=xci]
  ip/mig_config.prj[file_type=data]

The onlyif would be a new command which evaluates an arbitrary conditional expression. As variables we provide a set of "facts" about the system, which can be provided by different "facts" classes. The $vivado_version is just one example. This idea is taken from Puppet/facter, where this concept works really well.

@olofk , @wallento: what do you think?

Use Python distutils for installation

The module installation is a little overkill and unfriendly to Python users. Since there is nothing exotic that needs building, I suggest migrating to the standard python setup.py installation script.

This would then enable the project to be placed on PyPi and users could then install using the typical Python mechanism: pip install fusesoc.

"fusesoc build" returns zero result code when synthesis fails

Just a follow-up to openrisc/orpsoc-cores#105

When Analysis and synthesis fails for "fusesoc build xxx", fusesoc prints errors to the console, but then exits with the 0 exit code. It may confuse CI, because it requires special handling on it's side.

It happens due to the missing exit() call in

fusesoc/fusesoc/main.py

Lines 85 to 86 in 8c1bec7

	pr_err("Failed to build FPGA: " + str(e))

. Since the same behavior happens for other commands like pgm, maybe this behavior is "as designed".

Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")"; mismatched closing parenthesis . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")";  expecting "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
Error (10112): Ignored design unit "orpsoc_top" at orpsoc_top.v(36) due to previous errors File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 36
Info (12021): Found 0 design units, including 0 entities, in source file /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v
Info (12021): Found 1 design units, including 1 entities, in source file /fusesoc/build/sockit/src/sockit/rtl/verilog/rom.v
    Info (12023): Found entity 1: rom File: /fusesoc/build/sockit/src/sockit/rtl/verilog/rom.v Line: 36
Info (12021): Found 1 design units, including 1 entities, in source file /fusesoc/build/sockit/src/sockit/rtl/verilog/wb_intercon.v
    Info (12023): Found entity 1: wb_intercon File: /fusesoc/build/sockit/src/sockit/rtl/verilog/wb_intercon.v Line: 1
Info (144001): Generated suppressed messages file /fusesoc/build/sockit/bld-quartus/sockit.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 8 warnings
    Error: Peak virtual memory: 1147 megabytes
    Error: Processing ended: Thu Sep  8 12:29:15 2016
    Error: Elapsed time: 00:00:11
    Error: Total CPU time (on all processors): 00:00:18
Makefile:11: recipe for target 'map' failed
make: *** [map] Error 3
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in elf-loader�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_sdram_ctrl�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_altera_ddr_wrapper�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon-1.0�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in fifo-1.0�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in vlog_tb_utils�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ram_wb�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in stream_utils-1.0�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in elf-loader�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_sdram_ctrl�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_altera_ddr_wrapper�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon-1.0�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in fifo-1.0�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in vlog_tb_utils�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ram_wb�[0m
�[1;33mWARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in stream_utils-1.0�[0m
�[1;37mINFO:  Preparing jtag_tap�[0m
�[1;37mINFO:  Downloading olofk/jtag from github�[0m
�[1;37mINFO:  Preparing verilog-arbiter�[0m
�[1;37mINFO:  Downloading bmartini/verilog-arbiter from github�[0m
�[1;37mINFO:  Preparing verilog_utils�[0m
�[1;37mINFO:  Preparing vlog_tb_utils-1.0�[0m
�[1;37mINFO:  Preparing wb_bfm�[0m
�[1;37mINFO:  Preparing wb_intercon�[0m
�[1;37mINFO:  Preparing wb_common�[0m
�[1;37mINFO:  Preparing wb_ram-1.0�[0m
�[1;37mINFO:  Preparing wb_avalon_bridge�[0m
�[1;37mINFO:  Preparing adv_debug_sys�[0m
�[1;37mINFO:  Downloading olofk/adv_debug_sys from github�[0m
�[1;37mINFO:  Preparing altera_virtual_jtag�[0m
�[1;37mINFO:  Preparing mor1kx�[0m
�[1;37mINFO:  Downloading openrisc/mor1kx from github�[0m
�[1;37mINFO:  Preparing uart16550-1.5�[0m
�[1;37mINFO:  Downloading olofk/uart16550 from github�[0m
�[1;37mINFO:  Preparing elf-loader�[0m
�[1;37mINFO:  Preparing gpio�[0m
�[1;37mINFO:  Preparing vga_lcd�[0m
�[1;37mINFO:  Downloading olofk/vga_lcd from github�[0m
�[1;37mINFO:  Preparing i2c�[0m
�[1;37mINFO:  Downloading olofk/i2c from github�[0m
�[1;37mINFO:  Preparing sockit�[0m

�[1;31mERROR: Failed to build FPGA: "make" exited with an error code.
ERROR: See stderr for details.�[0m
[Pipeline] sh
[orpsoc-cores] Running shell script
+ mkdir system-sockit
+ mv fusesoc.log system-sockit
[Pipeline] step
Archiving artifacts
[Pipeline] }
[Pipeline] // node
[Pipeline] }
[Pipeline] // parallel
[Pipeline] End of Pipeline
Finished: SUCCESS

not able to load an elf file using the argument --elf-load

Dear Olof,
I tried installing fusesoc fresh on my crashed pc, and now, after installation, the elf-load argument is failing, throwing a fusesoc error as an unrecognised argument.

Reference:

jeebu@jeebu-desktop:~/openrisc/orpsoc-build$ ll
total 200
drwxrwxr-x 3 jeebu jeebu 4096 Jun 6 02:36 ./
drwxrwxr-x 9 jeebu jeebu 4096 Jun 5 13:50 ../
drwxr-xr-x 3 jeebu jeebu 4096 Jun 5 14:24 build/
-rw-rw-r-- 1 jeebu jeebu 81 Jun 5 11:12 fusesoc.conf
-rw-rw-r-- 1 jeebu jeebu 125 Jun 6 02:52 fusesoc.log
-rw-rw-r-- 1 jeebu jeebu 73 Jun 6 02:36 test.c
-rwxrwxr-x 1 jeebu jeebu 181449 Jun 6 02:36 test.elf*

jeebu@jeebu-desktop:~/openrisc/orpsoc-build$ fusesoc sim --force --elf-load=test.elf or1200-generic
usage: fusesoc [-h] [--cores-root CORES_ROOT] [--systems-root SYSTEMS_ROOT]

           {build,pgm,fetch,list-systems,system-info,list-cores,core-info,sim}
           ...

fusesoc: error: unrecognized arguments: --elf-load=test.elf
jeebu@jeebu-desktop:~/openrisc/orpsoc-build$

Thanks and Regards
Jeebu

local provider

In order to include .core files I propose to add a local provider that will look for files relative to the .core file and not download it. Proposed init section format

[provider]
name = local
root = _rootpath_

_rootpath_ is the relative path to the .core file location from which the other files form the filesets will be searched.
If this is implemented one can add the path to where one does RTL development to fusesoc.conf and from then on the cores will be found from the dev place there.
It should also be easy to write a release script that would then transform the .core file that later on can be pushed to fusesoc-cores.
Let me know what you think, if it sounds OK I may even try to implement it and provide pull request.

Background it that I am playing with some 8-bit cpus from freecores and I do plan to add .core in their code.

fusesoc sim de0_nano fails

I'm trying to simulate de0_nano using the icarus simulator. I'm getting the following messages:

INFO: Running /home/bernd/.local/share/orpsoc-cores/cores/elf-loader/check_libelf.sh
INFO: Running /home/bernd/.local/share/orpsoc-cores/systems/de0_nano/legacy_symlink.sh
/home/bernd/PycharmProjects/mix/workspace/de0_nano/build/de0_nano/src/de0_nano
/home/bernd/PycharmProjects/mix/workspace/de0_nano/build/de0_nano/src/de0_nano_0
Compiling /home/bernd/PycharmProjects/mix/workspace/de0_nano/build/de0_nano/src/elf-loader/elf-loader.c...
Compiling /home/bernd/PycharmProjects/mix/workspace/de0_nano/build/de0_nano/src/elf-loader/vpi_wrapper.c...
Making elf-loader.vpi from elf-loader.o vpi_wrapper.o...
Compiling /home/bernd/PycharmProjects/mix/workspace/de0_nano/build/de0_nano/src/jtag_vpi-r2/jtag_vpi.c...
Making jtag_vpi-r2.vpi from jtag_vpi.o...
warning: Found both default and timescale based delays. Use -Wtimescale to find the module(s) with no timescale.
../src/s25fl064p-1.7/s25fl064p.v:729: error: Unable to bind wire/reg/memory tdevice_DP' in orpsoc_tb.spi_flash.TDPr'
../src/s25fl064p-1.7/s25fl064p.v:738: error: Unable to bind wire/reg/memory tdevice_RES' in orpsoc_tb.spi_flash.TRESr'
../src/s25fl064p-1.7/s25fl064p.v:1352: error: Unable to bind wire/reg/memory tdevice_PP' in orpsoc_tb.spi_flash.pdone_process'
../src/s25fl064p-1.7/s25fl064p.v:1374: error: Unable to bind wire/reg/memory tdevice_WR' in orpsoc_tb.spi_flash.wdone_process'
../src/s25fl064p-1.7/s25fl064p.v:1390: error: Unable to bind wire/reg/memory tdevice_BE' in orpsoc_tb.spi_flash.erase'
../src/s25fl064p-1.7/s25fl064p.v:1394: error: Unable to bind wire/reg/memory tdevice_PE' in orpsoc_tb.spi_flash.erase'
../src/s25fl064p-1.7/s25fl064p.v:1398: error: Unable to bind wire/reg/memory tdevice_SE' in orpsoc_tb.spi_flash.erase'
7 error(s) during elaboration.
ERROR: Failed to build simulation model
ERROR: Failed to compile Icarus Simulation model

Please advise.
Thanks, Bernd

Unify system and cores root and change to providers style

Hi,

I am wondering why system_root and cores_root are distinct values. Shouldn't they be unified as one kind of "FuseSoC Catalogs".

Beside this I would suggest to extend those from file system directories to also some kind of provider.

Proposal: Add a fusesoc_catalogs variable to the config (and/or FUSESOC_CATALOGS to the environment), that is a colon-separated list of:

• Filesystem paths, format: /path/to/catalog
• http path, format https://github.com/olofk/coolip/master/tree/
• any other provider. I am thinking of a librecores.org API that can be used as a provider, so that librecores can be a catalog.

Once starting in this direction a more sophisticated dependency format should be possible. It should ideally allow for stuff like librecores:openrisc/[email protected] or some other cool stuff. But thats probably another issue then.

Best,
Stefan

Install error - ghdl

Install for new users fails. With the current version (installed using "pip") GHDL is not available but opa core into current repository try to load it. So, after install, all commands just show:
ValueError: Invalid value 'ghdl'. Allowed values are 'icarus', 'modelsim', 'verilator', 'isim', 'xsim'

Content of 9f4f539 must be pushed or a notice must be added to main README

unknown module <pfpu32_top>

Hi,
I'm using the fusesoc and I need to use the mor1kx with FPU, I found this posted here: https://github.com/openrisc/mor1kx.
I can't use this mor1kx on the fusesoc because when I synthesize the project on ISE, I have this error:
HDLCompiler:1654 - "/home/orpsoc/Documentos/Fusesoc/fusesoc/build/atlys/src/mor1kx-3.1/rtl/verilog/mor1kx_execute_alu.v" Line 512: Instantiating <u_pfpu32> from unknown module <pfpu32_top>
Can you help me?

windows support -- requires patch command

Windows systems are unlikely to have a commandline patch utility installed. So building any cores with patches will fail with

Error: Failed to call external command 'patch'

If the call to patch is replaced with native python that will bring fuse-soc closer to supporting windows

setup.py pyyaml dependency

setup.py is missing a dependency to pyyaml. If you do not have pyyaml installed then init will fail.

>fusesoc init
...
ImportError: No module named yaml

error when try to use fusesoc build atlys

Hey there,
I am trying to build core for atlys board, and I got this error:
WARN: File ../orpsoc-cores/systems/atlys/bench/orpsoc_tb.v does not exist
WARN: File ../orpsoc-cores/systems/atlys/bench/uart_decoder.v does not exist
ERROR: Failed to build FPGA: Command 'xtclsh' not found. Make sure it is in $PATH
While I have sourced setting64.sh and can run xtclsh directly from terminal.
I also added
export PATH=/opt/Xilinx/14.6/ISE_DS/common/bin/lin64:$PATH
export PATH=/opt/Xilinx/14.6/ISE_DS/ISE/bin/lin64:$PATH
to .bashrc.
Do you have a clue what is this issue about?
Thanks!
Karl

Add environment variable FUSESOC_ROOT

Hi,

it would be great if fusesoc did not only search for cores in the configured cores_root, but if the user can add further roots in an environment variable.

Best,
Stefan

Initialization/Installation Problem

Hello,

Running under Ubuntu 16.04LTS, Python 2.7.12, pip 9.0.0; I'm having a problem running the "fusesoc init" command in the installation instructions. I suspect that something got screwed up during installation. Here are the errors I receive:

VirtualBox:~/fusesoc$ fusesoc init
Traceback (most recent call last):
  File "/usr/local/bin/fusesoc", line 5, in <module>
    from pkg_resources import load_entry_point
  File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 2927, in <module>
    @_call_aside
  File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 2913, in _call_aside
    f(*args, **kwargs)
  File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 2940, in _initialize_master_working_set
    working_set = WorkingSet._build_master()
  File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 637, in _build_master
    return cls._build_from_requirements(__requires__)
  File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 650, in _build_from_requirements
    dists = ws.resolve(reqs, Environment())
  File "/usr/lib/python2.7/dist-packages/pkg_resources/__init__.py", line 834, in resolve
    raise VersionConflict(dist, req).with_context(dependent_req)
pkg_resources.ContextualVersionConflict: (attrs 16.2.0 (/usr/local/lib/python2.7/dist-packages), Requirement.parse('attrs<16.1.0'), set(['okonomiyaki']))
VirtualBox:~/fusesoc$

In fact, running any of the fusesoc commands seem to fail similarly, so I think something went wrong during my install or update (the output from the sudo pip install -e . phase says I have fusesoc 1.5).

Another note: when running the "sudo pip ..." commands, it kept giving me an error about permissions and suggested I use the "sudo -H ..." -H flag option. Which I did, so perhaps something got out of whack here.
Any help correcting my install is greatly appreciated :-)

Implement some way to at least warn about the system packages required by the HDL packages

The example in the README, wb_sdram_ctrl, actually requires development version of libelf (libelf-dev on Ubuntu) but if you don't have that, you will only see:

ERROR: Failed to build simulation model ERROR: Failed to compile VPI library elf-loader

In an e-mail discussion with @olofk he mentions he is aware of that but hasn't yet figured out a good way to handle this kind of stuff - since this is not a FuseSoC requirement per se - so I proposed an issue to initiate the discussion.

The least we could do of course would be to enable some messages to be printed by the package at build (like: This package requires the development version of libelf, which may be libelf-dev on your system. Make sure you have it installed.). I use that in our buildsystems where it is not trivial to explicitly check for something: of course this is not the best idea, but at least the developer would not need to bother people with questions if he can spot what's wrong himself.

Just writing it down in want of other propositions so far, I am sure there are better ways to handle it. Just thinking that actually having an example that can fail without a unambiguous warning/error message could potentially stop people who do 'let's download this and see what it is - not working - not useful' from giving FuseSoC a try. I happen to do exactly that if I'm not determined, the bad person I am ;)

windows installation problems

I ran into a few bumps trying out fusesoc, this is what I tried on a windows 10 machine with python 2.7.8

>pip install fusesoc
...
Successfully installed fusesoc-1.4
>fusesoc init
'fusesoc' is not recognized as an internal or external command,
operable program or batch file.

looks like setup.py put a file named fusesoc in C:/Python27/Scripts. Let's try running that.

>python C:\Python27\Scripts\fusesoc init
Traceback (most recent call last):
  File "C:\Python27\Scripts\fusesoc.py", line 25, in <module>
    from fusesoc.build import BackendFactory
  File "C:\Python27\Scripts\fusesoc.py", line 25, in <module>
    from fusesoc.build import BackendFactory
ImportError: No module named build

It's confused. I decided to try inside of a virtual environment.

>python venv/Scripts/fusesoc init
...
ImportError: No module named yaml

That got further. That one looks like a missing dependency

>pip install pyyaml
>python C:\Python27\Scripts\fusesoc init
...
INFO:  FuseSoC is ready to use!

UPDATE:

I think I figured out the issue: https://python-packaging-user-guide.readthedocs.io/en/latest/distributing/#scripts

"Although setup() supports a scripts keyword for pointing to pre-made scripts to install, the recommended approach to achieve cross-platform compatibility is to use console_scripts entry"

I'm working on a fix

simulation of mor1kx leads to compilation error

Hello,

I want to simulate the mor1kx module and the new branch predictor files (mor1kx_branch_predictor_simple.v) leads to a compilation error:

$$ fusesoc sim mor1kx-generic
...
INFO: Preparing mor1kx
INFO: Downloading openrisc/mor1kx from github
...
INFO: Preparing mor1kx-generic

INFO: Running /home//.local/share/orpsoc-cores/cores/elf-loader/check_libelf.sh
Compiling /home//workspace/openrisc/exe/build/mor1kx-generic/src/elf-loader/elf-loader.c...
Compiling /home//workspace/openrisc/exe/build/mor1kx-generic/src/elf-loader/vpi_wrapper.c...
Making elf-loader.vpi from elf-loader.o vpi_wrapper.o...
Compiling /home//workspace/openrisc/exe/build/mor1kx-generic/src/jtag_vpi-r2/jtag_vpi.c...
Making jtag_vpi-r2.vpi from jtag_vpi.o...
../src/mor1kx/rtl/verilog/mor1kx_branch_predictor_simple.v:19: syntax error
I give up.
ERROR: Failed to build simulation model
ERROR: Failed to compile Icarus Simulation model

This error also occurs, if I load an ELF-file

Do I something wrong?

Issue with modelsim simulation option

Hi, I tried to use the modelsim option. I had problems when fusesoc is compiling vpi modules for simulation, and simulation fails before starting. Failing occurs at linking

So I did some research and solved the issue by adding the compiler switch "-fno-stack-protector".

Now I am not sure if this problem is due to my system configuration. Probably gcc on this system has stack protection enabled, but then it tries linking a library that was compiled without stack protection, and linking fails.

Diff: http://pastebin.com/MQtdHs50

add svf-file generation

@olofk
Most of the time I use openocd to burn Altera's FPGA (e.g. I use Raspberry Pi for burning FPGA and can't run Quartus on it).
Can we add svf-file generation feature to fusesoc?
Just now I use this patch:

--- a/fusesoc/build/quartus.py
+++ b/fusesoc/build/quartus.py
@@ -8,7 +8,7 @@ class Quartus(Backend):
 
     MAKEFILE_TEMPLATE = """
 
-all: sta
+all: svf
 
 project: $(TCL_FILE)
        quartus_sh $(QUARTUS_OPTIONS) -t $(DESIGN_NAME).tcl
@@ -25,6 +25,9 @@ asm: fit
 sta: asm
        quartus_sta $(QUARTUS_OPTIONS) $(DESIGN_NAME)
 
+svf: sta
+       quartus_cpf -c -n p -q 2MHz -g 3.3 $(DESIGN_NAME).sof $(DESIGN_NAME).svf
+
 clean:
        rm -rf *.* db incremental_db
 """

I think that the patch is not perfect (e.g. hardcoding -q 2MHz -g 3.3 is a bad solution, I have to move this options to configuration file).

Any suggestions?

Verilator: Linker failures not captures

Verilator pipes the linker output through c++filt, so that the return code is not the linker error, but the c++filt return code. Maybe we can handle it here, but I suppose the proper way is in verilator itself.

Add system level tests to CI

In addition to a basic smoke test (#106), the CI should also exercise building, simulation, and synthesis.

To avoid the orpsoc-cores repo breaking these tests, a dummy test repo should be created. Just enough to exercise all of the fusesoc features.

To get good coverage, calls to 3rd party proprietary tools should probably be mocked. Open source simulators and synthesizers (icarus, ghdl, icestorm) can be installed and run from the ci.

Development with cores from fusesoc

In the readme it says fusesoc allows to create compile-time configurations. It is not clear to me how to do that.
Let's say that I want create a new project that uses the i2c core. How do I do that ? I tried to 'fusesoc fetch i2c' but this does not seem to give me the code.
Is this a use case not meant to be solved by fusesoc ?

How to use coregen provider ?

I am trying to use coregen from a core file using the coregen provider. This is the .core file:

CAPI=1
[main]
name = freecores.github.io:t80:Z80Rom
description = ROM for Z80 debug
simulators = isim

[provider coregen]
script_file = syn/xilinx/coregen/Z80Rom.xco
project_file = syn/xilinx/coregen/Atlys.cgp

For the t80 core I have the following depend in the [main] section:

[main]
...
depend = freecores.github.io:t80:Z80Rom

When trying to simulate the top core with isim the files are not generated:

$ fusesoc sim --build-only freecores.github.io:t80:T80
INFO:  Preparing freecores.github.io:t80:Z80Rom:0
INFO:  Preparing freecores.github.io:t80:T80:0

Running: /home/eda/software/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse TestBench -prj isim.prj -o fusesoc.elf 
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80_Pack.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/GBse.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T8080se.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80_ALU.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80a.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80_MCode.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80_Reg.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80sed.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80se.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80s.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T80.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/Z80.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/SSRAM.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/T16450.vhd" into library work
Parsing VHDL file "../src/freecores.github.io_t80_T80_0/rtl/vhdl/DebugSystem.vhd" into library work
ERROR:HDLCompiler:104 - "../src/freecores.github.io_t80_T80_0/rtl/vhdl/DebugSystem.vhd" Line 116: Cannot find <z80rom> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:854 - "../src/freecores.github.io_t80_T80_0/rtl/vhdl/DebugSystem.vhd" Line 33: Unit <struct> ignored due to previous errors.
VHDL file ../src/freecores.github.io_t80_T80_0/rtl/vhdl/DebugSystem.vhd ignored due to errors
ERROR: Failed to build simulation model
ERROR: Failed to compile Isim simulation model

DebugSystem.vhd is where the Z80Rom block is used

Build Linux

Hey there,
Maybe it's not the right place to ask, but all download links in http://opencores.org/or1k/Linux went invalid, while they were valid a few days ago. And I don't know to whom should I ask about this issue...

But I still have a kernel directory (I don't know which version) I downloaded before, and I built the vmlinux file. And I ran "fusesoc build atlys BOOTLOADER_BIN=vmlinux". It generated a opensoc_top.bit file, and I programmed it to atlys flash.
Is it the right way to do it?
From http://www.chokladfabriken.org/projects/orpsoc-atlys/files
I got a prebuilt FPGA image and when I program it to my board I can see graphic display from HDMI output. But for the opensoc_top.bit I can see nothing...

Sorry if it's not the right place to ask.. But I cannot find anything on the linux page..

Documentation in Sphinx

Hi all,

I'd like to propose that I set up some documentation in Sphinx for the project, incorporating what is there so far but making it possible to easily build HTML and PDF docs for everyone. Sphinx is the de-facto standard documentation system for Python, so I think it makes sense, and it's a known system with lots of manuals so people can contribute easily.

This way we could even push it to Read The Docs later - give it more exposure + get automagic builds available on the Web.

What do you think? @olofk I assume this is a question to you mostly :) ?

Warning: Unknown item 'name' in section 'vpi'

This warning appear whenever I use this command:

fusesoc list-systems

Then:

WARN:  Warning: Unknown item 'name' in section 'vpi'
WARN:  Warning: Unknown item 'name' in section 'vpi'
WARN:  Warning: Unknown item 'name' in section 'vpi'
Available systems:
de1
de0_nano

Make fusesoc more decentralized

Sorry if this is the wrong channel for this kind of request; would it be possible to design fusesoc to be more flexible in terms of where it sources repositories? Currently the only way (AFAIK) to hack on some of the components is to maintain a fork of orpsoc-cores and modify the system and core files there. Would it be possible to allow fusesoc to source system and core files from other repositories? So instead of a single repository holding all the dependency and build information, it could keep using that one repository, but users can create their own systems and cores in separate repositories that they can source from as well. This seems really rigid compared to the package management and build systems in a lot of other languages, where you can basically source packages from arbitrary repositories if you give the package manager the address of it

Sorry if this is already possible, and thank you for your time!

Add CI for smoke testing

discussed in #104, we should add continuous integration to fusesoc. There's different levels of testing that could be added, but this specific issue only tracks basic smoke testing

CI should install and execute init, list-cores, list-systems, and update
CI should get OS coverage on a linux system and a windows system.
CI should test multiple versions of python on each OS. Python 2.7 and 3.5 at minimum.

Issue with SECTION_MAP attribute

I've just updated to 15cf814 and I am seeing the following:

$ fusesoc list-cores
Traceback (most recent call last):
  File "/home/jules/git/fusesoc/bin/fusesoc", line 232, in 
    run(parsed_args)
  File "/home/jules/git/fusesoc/bin/fusesoc", line 167, in run
    cm.add_cores_root(config.cores_root)
  File "/home/jules/git/fusesoc/fusesoc/coremanager.py", line 64, in add_cores_root
    self.load_cores(os.path.expanduser(p))
  File "/home/jules/git/fusesoc/fusesoc/coremanager.py", line 53, in load_cores
    self.load_core(d, f)
  File "/home/jules/git/fusesoc/fusesoc/coremanager.py", line 30, in load_core
    self._cores[name] = Core(file)
  File "/home/jules/git/fusesoc/fusesoc/core.py", line 34, in __init__
    for s in section.SECTION_MAP:
AttributeError: 'module' object has no attribute 'SECTION_MAP'

By following the helpful advice of stekern here I was able to get this to work again. So I did something like:

$ make distclean
$ find . -name "*.pyc" | xargs rm

.. and list-cores worked again. However, probably the root cause of this should be identified?

Not sure if this is Python issue or what, but maybe a clean should clear away .pycs?

atlys build problem in dvi_gen_top.v

Hello,

I attempted to build the atlys system using the newer xilinx tools and got an error. Apparently the method used to divide the clock in dvi_gen_top.v is now illegal.

From Xilinx:
In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can occasionally enter a stuck state. Hence, it is not supported and an alternative implementation needs to be used.

The error from Xilinx ISE when building the atlys system:
ERROR:PhysDesignRules:2502 - Issue with pin connections and/or configuration on
block:<dvi_gen0/sysclk_div>:<BUFIO2_BUFIO2>. BUFIO2 has an invalid setting
of DIVIDE by 2. This setting is not supported. For more information please
see Answer Record 56113.

Thanks,

List of valid file types

At least a list of all file types should be kept and checked against.

Process "Place & Route" failed when building orpsoc for atlys board

Hi,

I was trying to build atlys system and I got some errors. My platform is fedora 20 and using Xilinx ISE 14.6. The following is a tail of the output error log:

3 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.

Generating Pad Report.

1 signals are not completely routed. See the orpsoc_top.unroutes file for a list of all unrouted signals.

WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not
completely routed in this design. See the "orpsoc_top.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.

WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 3 mins 14 secs
Total CPU time to PAR completion: 3 mins 16 secs

Peak Memory Usage: 995 MB

Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - 236 errors found.

Number of error messages: 0
Number of warning messages: 38
Number of info messages: 1

Writing design to file orpsoc_top.ncd

PAR done!

Process "Place & Route" failed
INFO:TclTasksC:1850 - process run : Generate Programming File is done.

Error build atlys

Hello!
This problem occurs when I try to build atlys.
When I check the .cache/fusesoc/* after the error, some of the directories are empity.

WARN: File /root/.cache/fusesoc/adv_debug_sys/rtl/verilog/adbg_wb_biu.v does not exist
WARN: File /root/.cache/fusesoc/adv_debug_sys/rtl/verilog/adbg_or1k_status_reg.v does not exist
WARN: File /root/.cache/fusesoc/adv_debug_sys/rtl/verilog/adbg_jsp_biu.v does not exist
...
INFO: Checking out http://github.com/openrisc/mor1kx/archive/master.tar.gz revision master to /root/.cache/fusesoc/mor1kx
http://github.com/openrisc/mor1kx/archive/master.tar.gz
Traceback (most recent call last):
File "/usr/local/bin/fusesoc", line 302, in
run(parsed_args)
File "/usr/local/bin/fusesoc", line 242, in run
args.func(args)
File "/usr/local/bin/fusesoc", line 51, in build
backend.configure()
File "/usr/local/lib/python2.7/dist-packages/fusesoc/build/ise.py", line 34, in configure
super(Ise, self).configure()
File "/usr/local/lib/python2.7/dist-packages/fusesoc/build/backend.py", line 57, in configure
core.setup()
File "/usr/local/lib/python2.7/dist-packages/fusesoc/core.py", line 98, in setup
if self.provider.fetch():
File "/usr/local/lib/python2.7/dist-packages/fusesoc/provider/github.py", line 26, in fetch
self._checkout(self.files_root)
File "/usr/local/lib/python2.7/dist-packages/fusesoc/provider/github.py", line 47, in _checkout
(filename, headers) = urllib.urlretrieve(url)
File "/usr/lib/python2.7/urllib.py", line 93, in urlretrieve
return _urlopener.retrieve(url, filename, reporthook, data)
File "/usr/lib/python2.7/urllib.py", line 239, in retrieve
fp = self.open(url, data)
File "/usr/lib/python2.7/urllib.py", line 207, in open
return getattr(self, name)(url)
File "/usr/lib/python2.7/urllib.py", line 344, in open_http
h.endheaders(data)
File "/usr/lib/python2.7/httplib.py", line 954, in endheaders
self._send_output(message_body)
File "/usr/lib/python2.7/httplib.py", line 814, in _send_output
self.send(msg)
File "/usr/lib/python2.7/httplib.py", line 776, in send
self.connect()
File "/usr/lib/python2.7/httplib.py", line 757, in connect
self.timeout, self.source_address)
File "/usr/lib/python2.7/socket.py", line 553, in create_connection
for res in getaddrinfo(host, port, 0, SOCK_STREAM):
IOError: [Errno socket error] [Errno -2] Name or service not known

ERRO 'xtclsh'

Hello,

So, I've been trying to build atlys with the command, '../fusesoc/bin/fusesoc build atlys', but he gives this erro, 'ERROR: Failed to build FPGA: Command 'xtclsh' not found. Make sure it is in $PATH'.
I don't know what can I do, I searched a lot but nothing help me.
Do you know what is it?

No obvious simple way to build the documentation

There's some documentation under doc/ but it's not obvious how to build it.

Probably what would be nice is being able to "make doc" or document the build procedure in INSTALL or readme.md.

What is FuseSoc?

Hello, I think this project lacks a README file. Without it, people like me can't figure what is it and what is it's purpose.

Failed to register cores root

I'm getting "ERROR: ~/downloads/orpsoc-cores/ is not a directory" but it certainly looks like one.

How to handle files that need generating?

Hi! I've been having a quick look around fusesoc and I was wondering if there's a way to specify a core that depends on parameters like one would for a Xilinx IP core for example. So rather than specifying the filenames in the core file, you'd specify a script to generate them, or something along those lines.

Perhaps this is obvious, but I had a look through the core files in orpsoc-cores and there didn't seem to be any file generation going on.

Can't "make install" after the lastest commit

As of the Tuesday commit which section was moved, I can't run "make install" without problem. Just "make" is OK, but an error appear with "make install":

Byte-compiling python modules...
__init__.pygithub.pyopencores.pyurl.py
Byte-compiling python modules (optimized versions) ...
__init__.pygithub.pyopencores.pyurl.py
make[2]: *** No rule to make target `fusesoc/section/__init__.py', needed by `install-sectionPYTHON'.  Stop.

Environment: Ubuntu 14.04, Python 2.7

Issue with github provider

Hello, I was getting a warning: unknown provider 'github' that blocked me from doing anything with the program since it aborted at that point, not finding any more cores.

Upon further inspection of source code I found that the problem here in my sistem was caused by github.py trying to load URLError from urllib.error which is fine on python 3 but the default is 2.7 here, so I made this modification : http://pastebin.com/V0cEcnkF .

I am having other problems with fusesoc but I'll leave that for other issue later. Thanks.

doc/quickstart.txt is outdated

https://github.com/olofk/fusesoc/blob/master/doc/quickstart.txt is no longer valid.
It should be updated or remove.