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.emacs.d

My emacs configuration

adapters

Common SOC interconnect protocols adapters for learning

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

bch_verilog

Verilog based BCH encoder/decoder

conv_arithmetic

A technical report on convolution arithmetic in the context of deep learning

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

ethernet_10ge_mac_sv_uvm_tb

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

general_aurora_intf

A simple example for using Aurora interface

gitignore

A collection of useful .gitignore templates

hello-world

Just a test

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

ies_tool_for_vivado

multiplier16x16

Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder

nand-flash-control

nand-flash-memory-controller-verification

open-rdma

RoCE v2 hardware implementation using Spinal HDL

openc910

OpenXuantie - OpenC910 Core

pcileech

Direct Memory Access (DMA) Attack Software

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

pulpino

An open-source microcontroller system based on RISC-V

roce

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

rtl_nand_flash_controller

spacemacs-private

My Spacemacs config

spinal-bootcamp

SpinalHDL-tutorial based on Jupyter Notebook

spinalhdl

Scala based HDL