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View Code? Open in Web Editor NEWNetFPGA 1G infrastructure and gateware
Home Page: www.netfpga.org
License: Other
NetFPGA 1G infrastructure and gateware
Home Page: www.netfpga.org
License: Other
+------------------------------------------------------------------------ | Author: Jad Naous <first initial last name at stanford period edu> | Description: Quick intro to NetFPGA +------------------------------------------------------------------------ CONTENTS: 1.0 Tree structure 2.0 Getting started with design 2.1 Using modules 2.2 Adding your own code 2.3 Overriding library code 2.4 Coregen 3.0 Environment setup 4.0 Simulation 5.0 Implementation 6.0 Running the hardware 6.1 Kernel Driver 6.2 Download 7.0 Contacts +----------------------------------------------------------------------- | 1.0 Tree structure +----------------------------------------------------------------------- The tree is structured as follows: netfpga | +------ bin (contains scripts for running simulations | and setting up the environment) | +------ lib (contains stable modules and common parts | | that are needed for simulation/synthesis/design) | | | +---- C (contains common software and code for reference designs) | | | +---- verilog (contains modules and files that can be reused for design) | | | | | +---- core (modules used by reference designs developed as part | | | of the NetFPGA design process) | | | | | +---- contrib (modules contributed by NetFPGA users) | | | +---- Makefiles (various makefiles for simulation and synthesis) | | | +---- Perl5 (contains common libraries to interact with | reference designs and aid in simulation) | +------ projects (contains user projects including the reference designs) | +---- reference_nic | | | +---- src (contains all the verilog code to be used for | | synthesis and simulation) | | | +---- synth (contains user .xco files to generate cores | | and Makefile to implement the design) | | | +---- sw (contains all software parts for the project) | | | +---- include (contains files that define macros and other | files to be included for simulation and/or synthesis) | +---- reference_router (reference 4-port IPv4 router) | +---- reference_switch (reference 4-port learning Ethernet switch) | +---- cpci (code for the Spartan device) | +---- cpci_reprogrammer (Virtex device to reprogram the Spartan) | +---- selftest (design to test all NetFPGA subsystems) | +---- dram_queue_test (verify the DRAM queue) | +---- dram_router (4-port IPv4 router using DRAM queues) | +---- scone (Software Component Of NEtfgpa) | +---- gui_scone (Java GUI for NetFPGA designs) | +---- wireshark_dissectors (Wireshark dissectors for NetFPGA packet types) The tree was design to enable modularity and common code sharing between the library and the user projects. The scripts used for synthesis and simulation should be flexible enough to allow the user to add her own code without changing or understanding how the scripts work. But this is outside the scope of this README. +----------------------------------------------------------------------- | 2.0 Getting started with Design +----------------------------------------------------------------------- The best way to learn how to use the tree is by example. If you look at the reference_nic project, you will notice several things: 1- The src directory is empty: This is because the project only uses library modules. 2- The sw directory is empty: This is because the software for the switch is also in the library 3- There is one file under include: lib_modules.txt. This file specifies the library modules to use. The best way to start a design is by copying either the reference_switch or the reference_router directories and adding/modifying files in the new directory. * 2.1 USING LIBRARY MODULES The lib_modules.txt file specifies a list of modules to use from the library. The modules are specified relative to the NetFPGA2.1-x.y/lib/verilog directory. You can choose to use different modules simply by changing the module path in the lib_modules.txt file. * 2.2 ADDING YOUR OWN CODE To add your own code, write the verilog files and put them in the src directory. You can also choose to partition them into separate directories under src. Note that only one level of hierarchy is usable. You can choose to use some, all, or even none of the original library modules. You can copy the library code and modify it in your project directory. Take out the library modules you are not using from the lib_modules.txt file. * 2.3 OVERRIDING LIBRARY CODE You might decide that you only need to change one file of a library module. You don't need to copy all the sources and remove the library module from lib_modules.txt. Simply copy the file you wish to modify to your project's src directory and modify it there. * 2.4 COREGEN If you need to use IP cores generated with Xilinx's Coregen, copy the .xco file that was generated to your project's synth directory. You don't need any of the other files. The scripts will take care of it. +----------------------------------------------------------------------- | 3.0 Environment setup +----------------------------------------------------------------------- The following environment variables need to be set: NF_ROOT - set to the root directory of the tree (NetFPGA2.1-x.y) NF_DESIGN_DIR - set to the project's directory (e.g. $NF_ROOT/projects/reference_nic) NF_WORK_DIR - set to the working directory (somewhere with lots of space) If you are running BASH you will then need to source ${NF_ROOT}/lib/bin/nf_profile. Otherwise, if you are running CSH then you will need to source ${NF_ROOT}/lib/bin/nf_cshrc. NOTE: Please make sure that the settings in these two files correspond to your setup. THE DEFAULTS WILL *NOT* WORK! +----------------------------------------------------------------------- | 4.0 Simulation +----------------------------------------------------------------------- To simulate your design, there are several libraries to help. Take a look at reference_router/verif/test_router_full to see how to use the perl library functions. To create your own testbench, copy one of the test_* directories and make sure its name has 3 parts test_major_minor. You can then modify the make_pkts file to your liking. The Perl libraries used live in lib/Perl5. You can add your own libraries your project's verif/src dir. To run the simulation, use the following command: nf_run_test.pl --major x --minor y To run it with a gui, add the --gui switch. Type nf_run_test.pl --help for full details. NOTE: coregen needs X. Make sure that you are running from a graphical console if IP cores are being built (for example the first time you are simulating or implementing a design.) +----------------------------------------------------------------------- | 5.0 Implementation +----------------------------------------------------------------------- To implement your design, cd to the synth directory and type make. If all goes well, you should end up with nf2_top_par.bit file that you can use to download to the FPGA. If problems occur, make sure that you have all the .xco files for the user generated IP cores in the synth directory. Make sure to look at nf2_top_par.twr to make sure that your design has passed timing checks. Also make sure to heed the note in section 4.0 above. +----------------------------------------------------------------------- | 6.0 Running the hardware +----------------------------------------------------------------------- To run the hardware, there are two steps: 1- load the kernel module 2- download the .bin file * 6.1 KERNEL DRIVER 1- cd to the lib/C/kernel directory, and type make. 2- as root, type insmod nf2.ko If all goes well, you should see nf2c0, nf2c1, nf2c2, and nf2c3 when you do ifconfig -a. If not, check that the card is plugged in properly and see if it is identified by the lspci command. * 6.2 DOWNLOAD 1- cd to lib/C/download and type make 2- as root, type nf_download /path/to/nf2_top_par.bin That's it! Your hardware is loaded on the device and should be working. Browse through the tools under lib/C/switch, lib/C/router, and lib/C/tools for tools to use to interact with real hardware. +----------------------------------------------------------------------- | 7.0 Contacts +----------------------------------------------------------------------- Public discussion forums: http://netfpga.org/forums/ Direct e-mail: [email protected] Web: http://netfpga.org/
i have download this packet_generator_1.1.1 on windows and unzip it get folder of netfpga,it including two folders (bidfiles,projects)and one LICENSE.,Then i update the ISE to 10.1SP3,
i copied packet_generator_1.1.1 from netfpga/projects to ~/netfpga/projects,and modify project.xml
replace core/io_queues/ethernet_mac
with
replace core/io_queues/ethernet_queue
contrib/ucsd/gig_eth_mac
when i go to ~/netfpga/projects/packet_generator/synth and type make
i get a error that i can not solve it!!!
can you help to solve it
thank you!!!!!!
Analysis of file <"nf2_top.prj"> succeeded.
================================================== =======================
Total memory usage is 126992 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Synthesis failed - see nf2_top.srp for details.
make: *** [nf2_top.ngc] 错误 1
Hi all,
I'm new to NetFPGA and would like to have a look at the flexrouter project and try it out. Unfortunately it seems that the source files are not available anymore. Is there any chance to reupload them?
Best regards,
Stefan
i run this program follow the https://github.com/NetFPGA/netfpga/wiki/TrafficClassification,but some error i can not solve it!
ex:when i run packetclassification.setup.sh, the computer will warn me,
:make ***[packetclassification] error
:can not delete *.mif files.
is there any way to fix it?
thanks
I am working on NetFPGA 1G CML.
My system is Centos 7. My ISE is 14.6 and Vivado is 15.2.
I have already succeeded in generating the bitfile of the project reference_nic_1g_cml.
Yet I got an error when try to generate the bitfile of reference_router_1g_cml at step 4.
I do follow the instructions of the readme:
https://github.com/NetFPGA/NetFPGA-1G-CML-live/tree/master/projects/reference_router_nf1_cml
The error message is as follows:
Could you please tell me where the problem lies?
Thank you very much.
The links for the schematics files in the wiki ( https://github.com/NetFPGA/netfpga/wiki/Guide#schematic-and-board-layout ) do not work.
Is there somehow a possibility to make those available?
Hi, noticed these links are down:
https://github.com/NetFPGA/netfpga/wiki/Guide#Schematic_and_board_layout
Can you update them?
Hi,
What distribution of Linux and version of the Xilinx tools should I be using?
I am getting too many errors, I am fixing too many of these errors and I keep running into problems and I hope somebody can just tell me:
"Use Fedora Core XX with Xilinx ISE 10.1 blah blah blah"
Most of the links from the documentation are broken, so if we can start piecing them back together we can fix this.
thank you,
https://forums.netfpga.org/ gives me this message:
Error 1014
CNAME Cross-User Banned
What happened?
You've requested a page on a website that is part of the Cloudflare network. The host is configured as a CNAME across accounts on Cloudflare, which is prohibited by security policy.
i run the applicantion of Traffic Classifier follow the (https://github.com/NetFPGA/netfpga/wiki/TrafficClassification).
but it remind me
make:***packetclass error
can not delete the *.mif files.
when i ran
cd classifier/src/bench/packetclassification && ./packetclassification.setup.sh
how can i slove it!
https://github.com/NetFPGA/netfpga/wiki/TrafficClassification#download-classifier
The link for the download is dead.
Hii,
Currently I am working on NetFPGA 1G platform. But while using all the 4 PHY ports, I am getting a problem that at a time only only 3 ports (any 3) gets power and there is no power in the 4th port. I want to know what is the power requirement for all the 4 ports in NetFPGA.
Is is SMPS problem? Kindly suggest me the possible solution.
Hii,
Currently, I am working on 1G NetFPGA platform. But while using 2 PHY ports, both ports have 1G speed, I have the problem that at a time one PHY port automatically adjusts to 10Mb(default speed). I still haven't found the cause for this problem. Can someone help me with this problem?
Thank you all.
I'm using Perl 5.14 and when I first used the register gen script, I noticed a lot of registers were valued NaN
. I did some digging and figured out that the log function was returning NaN
when a Math::BigInt
was passed into it.
I know you primarily support specific versions of software for NetFPGA development, but I thought maybe it would be of some use to someone if I posted it here.
Here's how I fixed it:
diff --git a/lib/Perl5/NF/Utils.pm b/lib/Perl5/NF/Utils.pm
index 8a77a7c..c19fcaf 100644
--- a/lib/Perl5/NF/Utils.pm
+++ b/lib/Perl5/NF/Utils.pm
@@ -30,7 +30,11 @@ sub log2 {
my $n = shift;
my $ret;
- eval { $ret = log($n) / log(2); };
+ if (ref($n) eq 'Math::BigInt') {
+ eval { $ret = $n->blog(2, 100); };
+ } else {
+ eval { $ret = log($n) / log(2); };
+ }
if ($@ ne '') {
my $err = $@;
chomp($err);
Those are the links to the mentioned wiki pages:
It's allways the section 'Obtaining the Tarball'.
Does anybody have a copy of those tarballs or contact to one of the authors of this project? As far as I saw, this stuff is not included in the netfpga repository.
Regards Jasper
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