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View Code? Open in Web Editor NEWA logic synthesis tool
License: MIT License
A logic synthesis tool
License: MIT License
Hi all,
May I know how can we check "mighty" command? Or any script suggest to optimize MIG?
Suppose I have an aig circuit, I try to convert it to aig and call "mighty" but there is a core dump.
also> read_aiger bar.aig
also> convert --aig_to_mig
also> mighty
mig i/o = 135/128 gates = 3238 level = 14
Segmentation fault (core dumped)
Any advice or guidance would be greatly appreciated.
Best regards,
Cherry
Hello,
I am trying to count the number of inverters in an MIG network is it possible?
Hello,
I was trying to get the xmg circuit from the verilog file, I noticed that the number of inverters are more than the number I got from the xmgcost command, I tried this with the EPFL benchmarks. I also tried to use xmginv to optimize the number of inverters, but I got the same verilog file in the output as before the inverter optimization.
without the xmginv
read_aiger $i; ps -a;
lut_mapping;
convert --aig_to_mig; ps -m;
convert --mig_to_xmg; ps -x;
write_verilog -x $destination_path/${strarr[5]}.v;
with the xmginv
read_aiger $i; ps -a;
lut_mapping;
convert --aig_to_mig; ps -m;
convert --mig_to_xmg; ps -x;
xmginv
write_verilog -x $destination_path/${strarr[5]}.v;
褚老师,
您好,我最近正在关注您的综合工具ALSO,想拿安装下这个工具实际跑一个电路的综合,但是没有看到相关的使用教程?想问下有简单的使用说明吗?工具里面包含哪些命令?每个命令如何使用?
还有2个问题:1、ALSO目前支持ASIC的综合吗?之前工艺库的mapping吗?2、ALSO里面有没有使用中间表达语言?比如yosys的RTLIL这种。
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