Contains all project code found on www.nandland.com
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License: MIT License
SPI Master for FPGA - VHDL and Verilog
License: MIT License
Contains all project code found on www.nandland.com
parameter SPI_MODE = 3; // CPOL = 1, CPHA = 1
parameter CLKS_PER_HALF_BIT = 4; // 6.25 MHz
parameter MAIN_CLK_DELAY = 2; // 25 MHz
parameter MAX_BYTES_PER_CS = 2; // 2 bytes per chip select
parameter CS_INACTIVE_CLKS = 10; // Adds delay between bytes
Here the actual clockspeed to me seems 250 MHz instead of 25 MHz. Also with a CLKS_PER_HALF_BIT of 4 this turns out to be 250 MHz/8 = 31.25 MHz maybe a zero was deleted from the MAIN_CLK_DELAY? So you meat to set it to 20 ns? if you want on the other hands the values in the comment it would require
parameter SPI_MODE = 3; // CPOL = 1, CPHA = 1
parameter CLKS_PER_HALF_BIT = 2; // 6.25 MHz
parameter MAIN_CLK_DELAY = 20; // 25 MHz
parameter MAX_BYTES_PER_CS = 2; // 2 bytes per chip select
parameter CS_INACTIVE_CLKS = 10; // Adds delay between bytes
I guess this line should be using the std_logic_1164 function "to_bitvector", shouldn't it?
Vivado claims an invalid type-conversion here otherwise
spi-master/VHDL/sim/SPI_Master_TB.vhd
Line 79 in 02ae8b3
Hi, I just ran a syntax check on your VHDL source code and it seems there is an error with the signal o_tx_ready. Essentially, you are reading an output signal, which should not be allowed. I haven't run the simulation though, so perhaps I might mistake. In that case, I do apologise.
Command used:
ghdl -a VHDL/source/*
Output:
VHDL/source/SPI_Master.vhd:161:10:error: port "o_tx_ready" cannot be read
VHDL/source/SPI_Master.vhd:187:10:error: port "o_tx_ready" cannot be read
The MAX_BYTES_PER_CS parameter setups the length of the r_TX_Count variable which determines the max amount of bytes per active level of chip select signal. As result the maximum number of bytes per CS becomes a 2^(len(r_TX_Count)). So the settings become like this:
MAX_BYTES_PER_CS | len(r_TX_Count) | Actual max bytes per CS |
---|---|---|
0 | 2 | 4 |
1 | 1 | 2 |
2 | 2 | 4 |
3 | 2 | 4 |
4 | 3 | 8 |
5 | 3 | 8 |
6 | 3 | 8 |
7 | 3 | 8 |
8 | 4 | 16 |
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