A guide covering Verilog & SystemVerilog including the applications, libraries and tools that will make you a better and more efficient developer by having a better understanding of how hardware works on the lowest level.
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Verilog is a Hardware Description Language(HDL) used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction.
SystemVerilog is an extension of Verilog with many of the verification features that allow engineers to verify the design using complex testbench structures and random stimuli in simulation.
Verilog HDL Basics training from Intel
SystemVerilog for Design and Verification
Verilog HDL Programming Courses on Udemy
Top Verilog Programming Courses on Coursera
Verilog course for Engineers on Technobyte
Verilog Tutorials and Courses on hackr.io
Designing With Verilog Certification from the Xilinx Learning Center
Learning Verilog for FPGA Development on LinkedIn Learning
SystemVerilog tutorial on ChipVerify
Apio is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your verilog designs.
IceStorm is a project that aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
Icestudio is a visual editor for open FPGA boards. Built on top of the Icestorm project using Apio.
EDA Playground is a online code for programming your Verilog projects.
PlatformIO is a professional collaborative platform for embedded development with no vendor lock-in. It provides support for multiplatforms and frameworks such as IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbed OS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V.
PlatformIO for VSCode is a plugin that provides support for the PlatformIO IDE on VSCode.
LLVM is a collection of modular and reusable compiler and toolchain technologies. It can be used to develop a front end for any programming language and a back end for any instruction set architecture(ISA). LLVM code representation is designed to be used in three different forms: as an in-memory compiler IR, as an on-disk bitcode representation (suitable for fast loading by a Just-In-Time compiler), and as a human readable assembly language representation.
Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
Clash compiler is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Verilator is an open-source SystemVerilog simulator and lint system.
Verilog to Routing(VTR) is a collaborative project to provide a open-source framework for conducting FPGA architecture and CAD Research & Development. The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
Cascade is a Just-In-Time Compiler for Verilog from VMware Research. Cascade executes code immediately in a software simulator, and performs compilation in the background. When compilation is finished, the code is moved into hardware, and from the user’s perspective it simply gets faster over time.
OpenTimer is a High-Performance Timing Analysis Tool for VLSI Systems.
- If would you like to contribute to this guide simply make a Pull Request.
Distributed under the Creative Commons Attribution 4.0 International (CC BY 4.0) Public License.
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