Nishit Bayen's Projects
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
Processor code, assembly code to noise filter and downsample an image, Instruction Set Architecture files available
A 2 in 1 robot able run on Bluetooth communication and able to avoid obstacle on it's own powered by "Vega processor" which is made in India indigenously by CDAC India
An 8-Bit CPU implemented in an FPGA
An algorithmic state machine verilog code for AES Encryption/Decryption Algorithm
Binary input BCD output in onboard 7-segment display of basys3
A Verilog code on Binary input and display output in 7 segment display in FPGA
A simple office Networking demo has been implemented using Cisco Packet Tracer to understand the networking topologies and working of corporate networks between machine to machine.
"Exploring Creative Solutions with an Arduino Microcontroller: From Beginner to Advanced Projects"
8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.
A web-based system for designing and simulating electronic (eSim) and Arduino circuits.
Full adder program using VHDL language
By this code you can control your home appliences by a nodemcu :
Developing IoT Projects with ESP32, published by Packt
Learn FPGA Programming, published by Packt
Modern Computer Architecture and Organization ā Second Edition, Published by Packt
a brief intro about myself using basic html
An animation is shown during hovering cursor
Config files for my GitHub profile.
A Code to find ip address of a nodemcu-ESP8266
React
Typescript
Django
Laravel
Facebook
Microsoft
Google
Alibaba
D3
Tencent