register_pipo_piso

Parallel in Parallel out, Parallel in Serial out Register Implementation with expansion Capabilities

riscv

RISC-V CPU Core (RV32IM)

roboschool

DEPRECATED: Open-source software for robot simulation, integrated with OpenAI Gym.

rtl-coding

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

rtl_design

sev_seg_fpga

its a seven segment display controller in FPGA which counts in ascending order

sev_seg_rev_fpga

A VERILOG code on seven segment display controller which counts in descending order

sine_function

Sine function generator and plotting it on serial plotter

square_wave

Square wave generator and receiver

t_flipflop-using-vhdl

T FlipFlop is created with frequency divider in basys3 FPGA board of family Artix-7 with VHDL language

tcp-calculator

A local server based TCP Calculator

verilog-systemverilog-guide

Verilog/SystemVerilog Guide

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

vlsi-fundamentals-a-practical-approach-education-kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

wifi_car

A code to operate a battery operated car over wifi control