dreamsourcelab / dslogic-hdl Goto Github PK

An open source FPGA design for DSLogic

License: GNU General Public License v2.0

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dslogic-hdl's Introduction

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README
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DSLogic-hdl is an Open-source hdl design for spartan-6 FPGA of DSLogic
DSLogic project: www.dreamsourcelab.com

Status
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DSLogic-hdl is in a usable state and has had official
tarball releases.


Copyright and license
---------------------

DSLogic-hdl is licensed under the terms of the GNU General Public
License (GPL), version 2 or later.


Website
-------

 http://www.dreamsourcelab.com

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dslogic-hdl's Issues

update request for HDL fw repositories

Would it be possible to update this repository with the source for https://github.com/DreamSourceLab/DSView/blob/master/DSView/res/DSLogicPro.bin, etc?
I'd like to learn more about the internal workings of this amazing piece of equipment!

Shifted the pins from 0-3 to 1-3,x

Hello.

I tested the DSLogic.
The firmware of the DSLogic basic is operating normally.

But, the firmware of the DSLogic pro isn't operating normally
The firmware is shifted the pins from 0-3 to 1-3,x.

The pin of no.0 isn't operating,
The pin of no.1 is operating as no.0 of DSView.
The pin of no.2 is operating as no.1 of DSView.
The pin of no.3 is operating as no.2 of DSView.
The next pin is NC(not connect), but, the pin is operating as no.3 of DSView.

Please check it.

Thanks and best regards.

Problem: sampling 50MHz signal at different rate

Here with I have attached dsl files, which holds the sampling of 50Mhz SPI CLK signal with setting of 16M samples @100MHz, 200MHz and 400MHz, its quite interesting to know that each file measures different SPI clock rate but at least @200mhz works fine but even then it varies in duty cycle from 50% to 75%, its weird behaviour.

I feel the hardware is stable enough till 25MHz signal beyond that its not promising, if you have different opinion, kindly share.

For the sake of attachment I have renamed the file to png, kindly save and rename it to .dsl

Is it a firmware issue or software issue?

dreamsourcelab / dslogic-hdl Goto Github PK

dslogic-hdl's Introduction

dslogic-hdl's People

Contributors

Stargazers

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dslogic-hdl's Issues

update request for HDL fw repositories

Shifted the pins from 0-3 to 1-3,x

Problem: sampling 50MHz signal at different rate

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DSLogic Schematic

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