coloquinte / moosic-yosys-plugin

Yosys plugin for logic locking and supply-chain security

Coriolis Etesian: an analytical VLSI placer

Etesian (formerly Coloquinte) is a framework for placing VLSI circuit. Coloquinte is now part of the Coriolis toolchain. If you are looking for an up-to-date version, please visit the official Coriolis repository.

It targets standard-cell digital circuits, optionally with pre-placed macroblocks. It is now a complete tool, handling all steps of a placement flow. It features exact and approximate wirelength models, and should be updated to do timing- and routing-driven optimization.

It is not standalone: no parsers; currently, it interfaces with the Coriolis CAD toolchain, but you you can follow the example main and interface it with your own tool. It is still a work in progress, and the optimization process could be significantly improved in the coming months. However, all tools are already competitive with other academic placers - and it is the only open source placer using analytical placement techniques.

Principle

Etesian is based on analytical placement: it performs continuous optimization of the objective function with a penalty accounting for overlap. This penalty is currently calculated from a legalized or partially legalized placement. It alternates between continuous optimization and legalization to reach a good solution, then perform local optimizations.

Tools

Global placement

Currently, the global placement is based on a common method: a quadratic local wirelength model that is optimized using conjugate gradient. It is extremely flexible, with the exact Steiner model as well as the classical star and bounding-box models, and takes advantage of parallelism.

Legalization

Legalization is performed in two steps: rough legalization, accounting for placement density, and exact legalization accounting for cell overlaps. Both should be beyond industrial level, although exact legalization only handles standard cells yet.

The rough legalizer models a 2D transportation problem that is optimized using various locally optimal algorithms. They may be run in parallel. The exact legalization places one cell at a time but is able to move previous cells to obtain better solution: it can handle extremely dense placements (>99%) with fixed macroblocks.

Detailed placement

The detailed placement optimizations look for topology (i.e. cell ordering) modifications, and optimize the positions for a given topology. They use specialized algorithms for position optimizations - most of them are not published yet -, and generally brute-force for topology modifications.

Runtime

For ~300,000 cells and a single core at 2 GHz, the runtimes are approximately (depending on solution quality):

• 10-30s per global placement iteration
• 10s for a rough legalization
• 3s to obtain a fully legal placement
• 400s to perform detailed placement

A typical placement run will usually feature 50 to 200 global placement iterations. Note that global placement and rough legalization can use multiple cores.

moosic-yosys-plugin's Issues

improve docs

Hi! nice presentation at FSiC2023!

Please improve the docs by adding a simple example command that shows logic locking in action.

Also, I just tested the plugin with oss-cad-suite, which might be worth including in your 'install instructions' section as it's a lot faster to install yosys that way.

Thanks,
Matt

Add Attacks ?

it would be interesting to have attacks such as the SAT attack at least.

Handling of multi-bit ports

Only single-bit wires are handled now. This is mostly OK for simple benchmarks, but breaks when modules have multi-bit ports

Improve the performance of Sat attack

The current Sat attack implementation uses Minisat provided by Yosys. It is quite limited compared to a more advanced Sat solver

Better error messages when logic locking is not applicable

We should at least have a useful error when the design is hierarchical or not synthetized

allow specify a given number of lock wires

can't see a way to control the number of lock wires

Multi-objective optimization over multiple metrics

Current metrics are area/delay/corruption estimates. We could still add corruption-related metrics + pairwise security.

Now we have to bridge those and add local-search algorithms to take care of the optimization.

Continuous integration on "official" ISCAS benchmarks

It's difficult to obtain a good source for the ISCAS benchmarks. At the moment, the best one I have (with .bench files) is https://pld.ttu.ee/~maksim/benchmarks/

For publication, it would be nice to switch CI to those (using yosys-abc -c "read_bench ...; write_verilog ..." for conversion) , and automate everything from there.

dump the lock wire key

after the design is locked and lock wires added, what is the key? how to find it?

Implementation of Anti-Sat methods

Implement Anti-Sat methods such as SKG-lock

Implement metrics from fault-based-analysis paper

It would be nice to implement the metrics used by "Fault Analysis-based Logic Encryption".

Theu use the number of test patterns that have an impact (NoP), times the total number of error (NoO), separated between 0 and 1 fault. This does not really make sense as it creates a quadratic version of the corruption (NoO only), but would be nice to have to compare to.

Corruption optimization is slow compared to FLL/KIP on very large designs

Using the greedy optimization on large designs, such as b18_1, can take more than an hour against just minutes for FLL/KIP. Find out if this can be improved.

Make the key port a bit vector

Currently there is one input per key-bit, which is not as user-friendly. The key should be a single input port

Build with OSS-CAD suite

It seems that yosys-config is not provided by OSS-CAD suite, so it's not possible to build with an OSS-CAD installation

improvement, use a bus for lock_key_

instead of adding many single wires, add a bus. Easier to adapt test benches
with lock_key[9:0]

ERROR: Multiple modules are selected.

hi, i have a project with multi verilog file and multi module, i use the moosic in a yosys script to encryption the project as below:

But I received the following error message

How should i do?

Handling of hierarchical modules

Currently, designs need to be flatten first. This would be nice to have

Avoiding slowdown of the circuit

This sounds a lot like you are adding a lot of delay into your design. It might make sense to calculate the critical path through the circuit first, and then apply this method only on all other pathes? (And only to apply as long as the modified pathes don't become the new critical path)

Flip-flops with a direct output cause combinatorial loops with Antisat

This can be seen with the following test:

yosys -m moosic -p "read_blif -sop blif/iscas89-s1196a.blif; flatten; synth; show; logic_locking -target outputs -nb-antisat 16 -antisat antisat -key 77777777777777777777777777777777777777; check"

User-specified locking key

Add a -key option, and use the cryptographic system RNG otherwise