Comments (13)
Thank you, that was quick!
Good point! It's done for the README. I'll check oss-cad-suite. Would you have an example of adding a plugin to it?
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Added the link to oss-cad-suite :)
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Hi Matt,
I just pushed a fix, and the command for TinyTapeout is working now :)
I opened a bunch of new issues to track the improvements I want to do in the close future. Don't hesitate to add new ones ;)
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make and make install works after oss-cad-suite installed
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If you want to tape out an example on TinyTapeout 04 I will give you a free slot.
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Thank you that's very nice !
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where's a good place to ask questions about this?
Is it possible to run this before synthesis? I'm thinkng the easiest way to tapeout would be add the logic locking, then write verilog. then run it through openlane.
Trying to run pre synth with this command:
yosys -m moosic-yosys-plugin -p 'read_verilog tt_um_seven_segment_seconds.v ; logic_locking -max-percent 5 -target corruption'
fails with:
2. Executing LOGIC_LOCKING pass.
Running logic locking with 10 test vectors, target 5.0% (0 cells out of 6).
ERROR: Assert `wire && wire->width == 1' failed in /opt/tabby/share/yosys/include/kernel/rtlil.h:1637.
tt_um_seven_segment_seconds can be found here: https://github.com/TinyTapeout/tt04-verilog-demo/blob/main/src/tt_um_seven_segment_seconds.v
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maybe it's a good idea to include a full demo design with a makefile that runs the logic lock and gets an output
bonus points for a github action that installs oss cad suite, compiles the plugin and runs a test automatically!
(inspiration: https://github.com/TinyTapeout/tt04-verilog-demo/actions/runs/5398183057/workflow)
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Indeed, it's only post-synthesis - I need to improve this error message. Difficult to do locking at the RTL level, since it's more difficult to get a logical model there.
So usually I do synth then logic_locking. I think a verilog export and back to open lane should work?
Asking here on GitHub issues is fine. If you prefer, we can talk by email too :)
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could you give an example yosys command?
this is failing post synth:
yosys -m moosic-yosys-plugin -p 'read_verilog tt_um_seven_segment_seconds.v decoder.v; synth -top tt_um_seven_segment_seconds; flatten; logic_locking -max-percent 5 -target corruption'
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This is a bug on my part on multi-bit module ports - all my benchmarks have single-bit ones :/ I'll get it fixed ASAP and get back to you once I get tinytapeout modules to work (probably tuesday next week as I'm on vacation until then).
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Thank you for the feedback :) It's starting to look a bit robust to actual designs ;)
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Related Issues (20)
- Continuous integration on "official" ISCAS benchmarks HOT 1
- Implement metrics from fault-based-analysis paper HOT 1
- Multi-objective optimization over multiple metrics HOT 1
- Add Attacks ? HOT 2
- Build with OSS-CAD suite
- ERROR: Multiple modules are selected. HOT 1
- Implementation of Anti-Sat methods HOT 1
- Improve the performance of Sat attack
- Better error messages when logic locking is not applicable HOT 2
- Flip-flops with a direct output cause combinatorial loops with Antisat HOT 2
- Corruption optimization is slow compared to FLL/KIP on very large designs HOT 1
- Avoiding slowdown of the circuit HOT 1
- User-specified locking key
- Handling of multi-bit ports
- Handling of hierarchical modules HOT 1
- Make the key port a bit vector
- dump the lock wire key HOT 1
- improvement, use a bus for lock_key_
- allow specify a given number of lock wires
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