Comments (1)
You can (kind of) do this with the ll_explore
command already, using -delay
as an objective and picking a solution with zero additional delay. It's not yet possible from the logic_locking
command, so I'm keeping this open until maybe I add it.
Note that the delay measure used is just the number of gates on the longest path: as far as I know there is not yet any timing analysis in Yosys.
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Related Issues (20)
- improve docs HOT 13
- Better error messages when logic locking is not applicable HOT 2
- User-specified locking key
- Handling of multi-bit ports
- Handling of hierarchical modules HOT 1
- Make the key port a bit vector
- dump the lock wire key HOT 1
- improvement, use a bus for lock_key_
- allow specify a given number of lock wires
- Continuous integration on "official" ISCAS benchmarks HOT 1
- Implement metrics from fault-based-analysis paper HOT 1
- Multi-objective optimization over multiple metrics HOT 1
- Add Attacks ? HOT 2
- Build with OSS-CAD suite
- ERROR: Multiple modules are selected. HOT 1
- Implementation of Anti-Sat methods HOT 1
- Improve the performance of Sat attack
- Flip-flops with a direct output cause combinatorial loops with Antisat HOT 2
- Corruption optimization is slow compared to FLL/KIP on very large designs HOT 1
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