albertschulz / poc

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

The PoC-Library

This library is published and maintained by Chair for VLSI Design, Diagnostics and Architecture - Faculty of Computer Science, Technische Universität Dresden, Germany
http://vlsi-eda.inf.tu-dresden.de

Table of Content:

1. Overview
2. Download
3. Requirements
4. Dependencies
5. Configuring PoC on a Local System (Stand Alone)
6. Integrating PoC into Projects
7. Using PoC
8. Updating PoC
9. References

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1 Overview

PoC - "Pile of Cores" provides implementations for often required hardware functions such as FIFOs, RAM wrapper, and ALUs. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.

TODO TODO TODO

Related repositories: PoC-Examples

2 Download

The PoC-Library can be downloaded as a zip-file (latest 'master' branch) or cloned with git clone from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See the Download wiki page for more details.

For HTTPS protocol use the URL https://github.com/VLSI-EDA/PoC.git or command line instruction:

cd <GitRoot>
git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC

For SSH protocol use the URL ssh://[email protected]:VLSI-EDA/PoC.git or command line instruction:

cd <GitRoot>
git clone --recursive ssh://[e-mail]:VLSI-EDA/PoC.git PoC

Note: The option --recursive performs a recursive clone operation for all linked git submodules. An additional git submodule init and git submodule update call is not needed anymore.

Note: The created folder <GitRoot>\PoC is used as <PoCRoot> in later instructions.

3 Requirements

The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or generating IP cores. We choose to use Python as a platform independent scripting environment. All Python scripts are wrapped in PowerShell or Bash scripts, to hide some platform specifics of Windows or Linux. See the Requirements wiki page for more details and download sources.

Common requirements:

• Programming languages and runtimes:

  • Python 3 (≥ 3.5):
    • colorama
    • py-flags

  All Python requirements are listed in requirements.txt and can be installed via:
  sudo python3.5 -m pip install -r requirements.txt

• Synthesis tool chains:

  • Altera Quartus-II ≥ 13.0 or
  • Lattice Diamond or
  • Xilinx ISE 14.7 or
  • Xilinx Vivado (restricted, see section 7.7)

• Simulation tool chains:

  • Aldec Active-HDL or
  • Mentor Graphics ModelSim Altera Edition or
  • Mentor Graphics QuestaSim or
  • Xilinx ISE Simulator 14.7 or
  • Xilinx Vivado Simulator ≥ 2016.1 or
  • GHDL ≥ 0.34dev and GTKWave ≥ 3.3.70

Linux specific requirements:

• Debian specific:
  • bash is configured as /bin/sh (read more)
    dpkg-reconfigure dash

Windows specific requirements:

• PowerShell 4.0 (Windows Management Framework 4.0)
  • Allow local script execution (read more)
    Set-ExecutionPolicy RemoteSigned
  • PowerShell Community Extensions 3.2 (pscx.codeplex.com)

4 Dependencies

The PoC-Library depends on:

• Cocotb - A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
• OS-VVM - Open Source VHDL Verification Methodology.
• VUnit - An unit testing framework for VHDL.

All dependencies are available as GitHub repositories and are linked to PoC as git submodules into the <PoCRoot>\lib\ directory.

5 Configuring PoC on a Local System (Stand Alone)

To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool chains. The following commands start a guided configuration process. Please follow the instructions. It's possible to relaunch the process at every time, for example to register new tools or to update tool versions. See the Configuration wiki page for more details.

All Windows command line instructions are intended for Windows PowerShell, if not marked otherwise. So executing the following instructions in Windows Command Prompt (cmd.exe) won't function or result in errors! See the Requirements wiki page on where to download or update PowerShell.

Run the following command line instructions to configure PoC on your local system.

cd <PoCRoot>
.\poc.ps1 configure

Note: The configuration process can be re-run at every time to add, remove or update choices made.

If you want to check your installation, you can run one of our testbenches as described in tb/README.md

6 Integrating PoC into Projects

The PoC-Library is meant to be integrated into HDL projects. Therefore it's recommended to create a library folder and add the PoC-Library as a git submodule. After the repository linking is done, some short configuration steps are required to setup paths and tool chains. The following command line instructions show a short example on how to integrate PoC. A detailed list of steps can be found on the Integration wiki page.

6.1 Adding the Library as a git submodule

The following command line instructions will create the folder lib\PoC\ and clone the PoC-Library as a git submodule into that folder.

cd <ProjectRoot>
mkdir lib | cd
git submodule add [e-mail]:VLSI-EDA/PoC.git PoC
cd PoC
git remote rename origin github
cd ..\..
git add .gitmodules lib\PoC
git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)."

6.2 Configuring PoC

The PoC-Library needs to be configured.

cd <ProjectRoot>
cd lib\PoC\
.\poc.ps1 configure

6.3 Creating PoC's my_config and my_project Files

The PoC-Library needs two VHDL files for it's configuration. These files are used to determine the most suitable implementation depending on the provided platform information. Copy these two template files into your project's source folder. Rename these files to *.vhdl and configure the VHDL constants in these files.

cd <ProjectRoot>
cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl
cp lib\PoC\src\common\my_project.vhdl.template src\common\my_project.vhdl

my_config.vhdl defines two global constants, which need to be adjusted:

constant MY_BOARD            : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys
constant MY_DEVICE           : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3

my_project.vhdl also defines two global constants, which need to be adjusted:

constant MY_PROJECT_DIR      : string := "CHANGE THIS"; -- e.g. d:/vhdl/myproject/, /home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. WINDOWS, LINUX

6.4 Compile shipped Xilinx IP cores (*.xco files) to Netlists

The PoC-Library is shipped with some pre-configured IP cores from Xilinx. These IP cores are shipped as *.xco files and need to be compiled to netlists (*.ngc files) and there auxillary files (*.ncf files; *.vhdl files; ...). This can be done by invoking PoC's Service Tool through one of the provided wrapper scripts: poc.[sh|ps1].

The following example compiles PoC.xil.ChipScopeICON_1 from <PoCRoot>\src\xil\xil_ChipScopeICON_1.xco for a Kintex-7 325T device into <PoCRoot>/netlist/XC7K325T-2FFG900/xil/.

cd <PoCRoot>/netlist
..\poc.ps1 coregen PoC.xil.ChipScopeICON_1 --board=KC705

7 Using PoC

The PoC-Library is structured into several sub-folders naming the purpose of the folder like src for sources files or tb for testbench files. The structure within these folders is always the same and based on PoC's sub-namespace tree.

Main directory overview:

• lib - Embedded or linked external libraries.
• netlist - Configuration files and output directory for pre-configured netlist synthesis results from vendor IP cores or from complex PoC controllers.
• py - Supporting Python scripts.
• sim - Pre-configured waveform views for selected testbenches.
• src - PoC's source files grouped into sub-folders according to the sub-namespace tree.
• tb - Testbench files.
• tcl - Tcl files.
• temp - A created temporary directors for various tools used by PoC's Python scripts.
• tools - Settings/highlighting files and helpers for supported tools.
• ucf - Pre-configured constraint files (*.ucf, *.xdc, *.sdc) for supported FPGA boards.
• xst - Configuration files to synthesize PoC modules with Xilinx XST into a netlist.

7.1 Common Notes

All VHDL source files should be compiled into the VHDL library PoC. If not indicated otherwise, all source files can be compiled using the VHDL-93 or VHDL-2008 language version. Incompatible files are named *.v93.vhdl and *.v08.vhdl to denote the highest supported language version.

7.2 Standalone

7.3 In Altera Quartus II

7.4 In GHDL

7.5 In ModelSim/QuestaSim

7.6 In Xilinx ISE (XST and iSim)

The PoC-Library was originally designed for the Xilinx ISE design flow. The latest version (14.7) is supported and required to explore PoC's full potential. Don't forget to activate the new XST parser in new projects and to append the IP core search directory if generated netlists are used.

1. Activating the New Parser in XST
   PoC requires XST to use the new source file parser, introduced with the Virtex-6 FPGA family. It is backward compatible.

   -> Open the XST Process Property window and add -use_new_parser yes to the option Other XST Command Line Options.

2. Setting the IP Core Search Directory for Generated Netlists
   PoC can generate netlists for bundled source files or for pre-configured IP cores. These netlists are copied into the <PoCRoot>\netlist\<DEVICE> folder. This folder and its subfolders need to be added to the IP core search directory.

   -> Open the XST Process Property window and append the directory to the -sd option. -> Open Translate Process Property and append the paths here, too.

   D:\git\PoC\netlist\XC7VX485T-2FFG1761|      ↩
   D:\git\PoC\netlist\XC7VX485T-2FFG1761\xil|  ↩
   D:\git\PoC\netlist\XC7VX485T-2FFG1761\sata
   

   Note: The IP core search directory value is a | seperated list of directories. A recursive search is not performed, so sub-folders need to be named individually.

7.7 In Xilinx Vivado (Synth and xSim)

The PoC-Library has no full Vivado support, because of the incomplete VHDL-93 support in Vivado's synthesis tool. Especially the incorrect implementation of physical types causes errors in PoC's I/O modules.

Vivado's simulator xSim is not affected.

Experimental Vivado Branch: We provide a vivado branch, which can be used for Vivado synthesis. This branch contains workarounds to let Vivado synthesize our modules. As an effect some interfaces (mostly generics have changed).

8 Updating PoC

The PoC-Library can be updated by using git fetch:

cd <GitRoot>\PoC
git fetch
# review the commit tree and messages, using the 'treea' alias
git tree --all
# if all changes are OK, do a fast-forward merge
git merge

9 References

• PoC-Examples:
  A list of examples and reference implementations for the PoC-Library
• The Q27 Project:
  27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
• PicoBlaze-Library:
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
• PicoBlaze-Examples:
  A SoFPGA reference implementation, based on the PoC-Library and the PicoBlaze-Library.

If you are using the PoC-Library, please let us know. We are grateful for your project's reference.