yuravg / uvm_tb_cross_bar

SystemVerilog UVM testbench example

SystemVerilog UVM testbench example

uvm_tb_cross_bar is my a SystemVerilog UVM example. It has DUT, testbench and scripts to run simulation.

DUT

A cross_bar project is used as DUT, this is just a bus switcher(specification). Used my implementation of this design.

DUT implementation is located in the rtl directory.

RTL synthesis

For RTL synthesis is used Intel Quartus Prime, example is located in the quartus directory.

|-rtl/

Testbench

The testbench has bus and cross-bar UVC.

Bus UVC has agent and sequences.

Cross-bar UVC has agent, connecting layer and sequences. The layer provides connectivity cross-bar and bus UVC.

Env has scoreboard and connect cross-bar agents. The scoreboard is checking results of each tests.

TB provides connection RLT to UVM Test.

Each Test connects Env to DUT and runs required virtual_sequences. The result of all sequences is checked using scoreboard.

|-agents/
| |_bus_uvc/
| |_cross_bar_uvc/
-uvm_tb/
  |_env/
  |_tb/
  |_tests/
  |_virtual_sequences/

Simulation

To run simulation of this example used Mentor Graphic’s QuestaSim or ModelSim simulator.

Directory sim contains files to run simulation.

Following examples of commands to be run from the sim directory.

|-sim/

Simulation launch

To run the simulation used console and make-file.

To get list of available commands or list of tests should run following command from console:

$ make help

Run complete verification

Run command from console:

$ make all_tests

The results of each test and a summary of all the tests are displayed in the console.

Each test writes a log and report files: <test_name>.log, <test_name>.log.rpt (report file - it is just reformatted the log file).

Log-file output example

Rpt-file output example

Summary example

Run some test

At this example there are following ways to run tests:

1. run test in console(without GUI)
2. run test with GUI from console
3. run test from GUI

1. Run test in console(without GUI)

To run test just run command from console:

$ make <test_name>

<test_name> - name from list of tests

2. run test with GUI from console

Should set empty environment variable VSIM_MODE, and run test in console (example for BASH):

$ export VSIM_MODE=''
$ make <test_name>

or

$ make <test_name> VSIM_MODE=''

<test_name> - name from list of tests

3. run test from GUI

Run ModelSim/QuestaSim, load aliases, run test.

• Run ModelSim/QuestaSim in sim directory

$ vsim `pwd` &

• run in ModelSim/QuestaSim Transcript window

do alias.do

• run test

run_<test_name>

Screenshots

Mentor Graphic’s QuestaSim wave

License

This project is licensed under the MIT License. If not, see https://www.opensource.org/licenses/MIT

uvm_tb_cross_bar's Issues

Supporting windows for running test from GUI

By replacing the following code in `sim/Makefile , the tests can be run in Windows.

ifeq ($(OS),Windows_NT)
# Windows-specific
wlib:
    @if not exist work ( \
        vlib work \
    )
    vmap work work
else
# Linux-specific
wlib:
    @-if [ ! -d work ] ; then \
    vlib work;              \
    fi
    vmap work work
endif