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An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。

Home Page: https://gitee.com/wangxuan95/FPGA-RMII-SMII

License: GNU General Public License v3.0

Batchfile 0.67% Verilog 99.33%
fpga verilog rtl ethernet 100m-ethernet mii rmii smii phy ethernet-phy

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  • systemverilog verilog bluespec c python csharp

  • iverilog quartus vivado arduino lceda

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1847123212 luweiqi silicon-wzh honestqiao paultcn hushunkui xinghuaman baoyoubing nijmeijer tomhuangsrc channingch ahchit suraj1singh2460 openfpga666 lmb3939

fpga-rmii-smii's Issues

关于alexforencich的以太网项目仿真

WangXuan你好！
非常开心能够在Github上面看到一个关于alex的以太网关联项目！最近十来天为了这个项目很是焦头烂额，alex在项目下只说了需要的工具和环境，却没有明确的指出需要如何组织和使用，几乎摸着石头过河的做了很久。第一次真正接触Verilog大一点的项目就是alex的以太网，又是自己一个人在做，实验室的师兄师姐也都没有用过python来写仿真文件，所以冒昧的想要来向你请教。
我看了你写的iverilog的使用指南，受益匪浅，也相见恨晚，很快的就把你的工程跑出来了。短短的一篇文章如果早看到的话最少可以节约两天时间了。所以能否请教一下您，alexforencich/verilog-ethernet项目的仿真您有相关的指南吗？我已经按照testing下的内容安装好了相关的工具和环境。
真诚而热切的希望能够得到您的回复！

MII-SGMII

Dear Dr. Wang, I'm a first year master's student, what modification should I make if I want to achieve the conversion from MII to SGMII?

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