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License: MIT License
Simple SoC in VHDL with full toolchain and custom board.
License: MIT License
CPU need access to larger data space. This space can be provided by external SDRAM. We need to write SDRAM driver for IS42S16160B that is located on DE0 nano board.
SDRAM datasheet: IS42S16160B.pdf
There are few bugs in IO board design.
There is probably problem with gitignore. It is look like git is ignoring all changes of files in fpga/src directory.
There is bug in linker somewhere. In one file I have
.IMPORT main
CALL main
in second file
.EXPORT main
main:
linker is not able to deal with this properly.
MARK-II need I2S bus driver to be able produce sound on new board.
Consider support for cursor in VGA driver. VRAM is now consist of 15 bits wide words, Use bit 16 to implement "cursor enable". It should be implemented as blinking underscore.
There is something terrible wrong with labels in macros. Trying to compile this code
#macro jump
OR R0 R0 R0
label:
OR R0 R0 R0
BZ R0 label
#endmacro
OR R1 R1 R1
$jump
And horrible things will happen:
$ m2-assembler test.asm
Traceback (most recent call last):
File "/opt/MARK_II_tools/bin/m2-assembler", line 773, in <module>
main()
File "/opt/MARK_II_tools/bin/m2-assembler", line 759, in main
a.pass0()
File "/opt/MARK_II_tools/bin/m2-assembler", line 56, in pass0
self.t.parse(self.mainFileName)
File "/opt/MARK_II_tools/src/assembler/tokenizer.py", line 127, in parse
self.load_file(p)
File "/opt/MARK_II_tools/src/assembler/tokenizer.py", line 286, in load_file
macro_item.invoke(self.parser_buffer, given_args, line_counter, file_name)
File "/opt/MARK_II_tools/src/assembler/tokenizer.py", line 96, in invoke
found_arg, value_arg = self.find_arg_value(given_args, line_token)
File "/opt/MARK_II_tools/src/assembler/tokenizer.py", line 66, in find_arg_value
return found, given_args[counter]
IndexError: list index out of range
There is something terribly wrong in tokenizer.py.
Please check how assembler deal with negative values as arguments. Negative values should be probably emited by compiler directly in hexadecimal form.
Implement in-line assembler into mark vbcc backend. This should be done easy. Also implement interrupt handlers.
It is necessary to add support for transmitting using PS/2. CPU need to talk with keyboard bidirectionally.
Probably bug in vbcc backend:
char strA[2][32] = {{"Hello world A!"}, {"Hello World B!"}};
char *strB[2];
int main(){
strB[0] = &strA[0][0];
strB[1] = &strA[1][0];
return 0;
}
strB is array of pointers to char, vbcc compile it into:
.EXPORT main
main:
PUSH R13
OR R0 SP R13
PUSH R1
PUSH R2
PUSH R3
PUSH R4
MVIA R1 strA
ST R1 strB
MVIA R1 strA
MVIA R2 strB
MVIA R3 1
ADD R2 R3 R2
STI R1 R2
OR R0 R0 R5
L_1:
POP R4
POP R3
POP R2
POP R1
OR R0 R13 SP
POP R13
RET
.EXPORT strA
strA:
.DAT 72
.DAT 101
.DAT 108
.DAT 108
.DAT 111
.DAT 32
.DAT 119
.DAT 111
.DAT 114
.DAT 108
.DAT 100
.DAT 32
.DAT 65
.DAT 33
.DAT 0
.DS 17
.DAT 72
.DAT 101
.DAT 108
.DAT 108
.DAT 111
.DAT 32
.DAT 87
.DAT 111
.DAT 114
.DAT 108
.DAT 100
.DAT 32
.DAT 66
.DAT 33
.DAT 0
.DS 17
.EXPORT strB
strB:
.DS 2
in main function, after function head, vbcc try to load address of strA[0][0] into strB[0], and that is correct, but it will load same strA[0][0] address into strB[1], in strB[1] should be strA[1][0] instead
I tested it with gcc and code worked as expected.
Signal int_accept from instruction decoder is asynchronous, but should be synchronous as others signals from ID.
It would be nice to have simple random number generator, for example something like free running linear feedback shift register. It may be necessary to have one for generating random seeds for pseudo random numbers by c library.
Simple overview of Standard peripheral library should be great. Also add some examples of using it.
There is a lot of I2C devices on the new board. MARK-II need driver for this bus.
According discussion at reddit there is priority encoder in comparison unit. But this priority encoder is unwanted. Suggested solution is use of case statement.
It should be possible read from VRAM too. Implement it!
CPU core should be improved, but should be compatible with old one.
What new core should be able:
There is a lot of place to speed up CPU, ideal should be 50MHz or 100MHz. Just now CPU is running at 50MHz on Cyclone IV, and at 25MHz on low cost MAX10. Things that can be done to speed up:
MARK-II need some SPI driver that will allow communication with NOR Flash IC on the board. If it can work with SD card too, it would be nice.
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