Do not support the constant shift about vtr-verilog-to-routing

[fresh-eggs]

Implementation of such a feature is currently being investigated by Zack and Panos.

[mflawn]

Still outstanding issue, see attached the file to reproduce:

a25_decode_fix.v.txt

Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation) 
==========================
Detected Top Level Module:      a25_decode
==========================
-------------- 
Odin has decided you have failed ;)

ERROR (1):NETLIST_ERROR (File: a25/a25_decode_fix.v) (Line number: 1239) Odin only supports constant shifts at present

                                                        (instruction[15:0] & (1'd1 << instruction[19:16]));
ASSERT FAILED:
        @[/mnt/c/Users/casa/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp]create_operation_node::4213  
Aborted (core dumped)

[jeanlego]

closing since #1560 add variable shift support