verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

Welcome to Verilator

Welcome to Verilator, the fastest Verilog/SystemVerilog simulator. Accepts Verilog or SystemVerilog Performs lint code-quality checks Compiles into multithreaded C++, or SystemC Creates XML to front-end your own tools
	Fast Outperforms many closed-source commercial simulators Single- and multithreaded output models
Widely Used Wide industry and academic deployment Out-of-the-box support from Arm and RISC-V vendor IP
	Community Driven & Openly Licensed Guided by the CHIPS Alliance and Linux Foundation Open, and free as in both speech and beer More simulation for your verification budget
Commercial Support Available Commercial support contracts Design support contracts Enhancement contracts

What Verilator Does

Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code.

These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper file, to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators.

Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend Icarus Verilog for classwork). However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of designs, Verilator is the tool for you.

Performance

Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a single thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators).

Verilator has typically similar or better performance versus closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator, Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus, Verilator gives you the best simulation cycles/dollar.

Installation & Documentation

For more information:

• Verilator installation and package directory structure
• Verilator manual (HTML), or Verilator manual (PDF)
• Subscribe to Verilator announcements
• Verilator forum
• Verilator issues

Support

Verilator is a community project, guided by the CHIPS Alliance under the Linux Foundation.

We appreciate and welcome your contributions in whatever form; please see Contributing to Verilator. Thanks to our Contributors and Sponsors.

Verilator also supports and encourages commercial support models and organizations; please see Verilator Commercial Support.

Related Projects

• GTKwave - Waveform viewer for Verilator traces.
• Icarus Verilog - Icarus is a full-featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may.

Open License

Verilator is Copyright 2003-2024 by Wilson Snyder. (Report bugs to Verilator Issues.)

Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details.

verilator's Issues

3.663 installation problem; missing bisonfix script

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Author Name: Guenter Dannoritzer
Original Redmine Issue: 7 from https://www.veripool.org
Original Date: 2008-05-08
Original Assignee: Wilson Snyder (@wsnyder)

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When calling make during the installation process of verilator 3.663 the src/Makefile_obj.in requires a bisonfix script to run, that is not part of the latest verilator 3.663 source package.

See the following lines of the src/Makefile_obj.in, starting at line 255:

1. Have only one output file in this rule to prevent parallel make issues
y.tab.c: verilog.y $(HEADERS)
	@echo "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer."
	${YACC} ${YFLAGS} $<
	mv y.tab.c y_pregen.tab.c && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.c > y.tab.c
	mv y.tab.h y_pregen.tab.h && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.h > y.tab.h

install man page in $prefix fails

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Author Name: Holger Wächtler
Original Redmine Issue: 20 from https://www.veripool.org
Original Date: 2008-07-14
Original Assignee: Wilson Snyder (@wsnyder)

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/bin/sh ./mkinstalldirs /Users/holger/verilog-stuff/3rdparty/share/man/man1
for p in verilator.1 ; do \
  /usr/bin/install -c $p /Users/holger/verilog-stuff/3rdparty/share/man/man1/$p; \
done
install: verilator.1: No such file or directory
make[2]: *** [installman] Error 71
make[1]: *** [/Users/holger/verilog-stuff/3rdparty/bin/verilator] Error 2
make: *** [i_mul.verilated] Error 2

$fopen() & friends don't work as expected...

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Author Name: Holger Wächtler
Original Redmine Issue: 21 from https://www.veripool.org
Original Date: 2008-07-14
Original Assignee: Wilson Snyder (@wsnyder)

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file test.vt:

module testbench;
         integer infile, outfile, count, a;
         initial begin
                 infile = $fopen("test.in", "r");
                 outfile = $fopen("test.out", "w");
                 $display("count == %d, infile %d, outfile %d", count, infile, outfile);
                 count = $fscanf(infile, "%d\n", a);
                 $display("count == %d, infile %d, outfile %d", count, infile, outfile);
                 $fwrite(outfile, "# a\n");
                 $fwrite(outfile, "%d\n", a);
                 $fclose(infile);
                 $fclose(outfile);
                 $finish;
         end
endmodule

file test.in:

1
2
3

Icarus Verilog output:

./test.vvp
count ==           x, infile -2147483645, outfile -2147483644
count ==           1, infile -2147483645, outfile -2147483644

test.out generated when simulating using Icarus Verilog:

1. a
           1

Verilator creates empty output file and this command line output:

./test.verilated 
count ==           0, infile           0, outfile           0
count ==           0, infile           0, outfile           0

verilator_includer installed to two locations

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Author Name: Lane Brooks
Original Redmine Issue: 48 from https://www.veripool.org
Original Date: 2009-01-09
Original Assignee: Wilson Snyder (@wsnyder)

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The verilator_includer perl file is being installed to both /usr/bin/verilator_includer and /usr/share/verilator/bin/verilator_includer. Based on my experiments to remove either one, it seems the one in /usr/share/verilator/bin is the critical one. I am only reporting this as an issue in case you want to clean it up. For the Fedora rpm, I am deleting the one put in /usr/bin because of requests not to have duplicate files. My verilator simulations run just fine without the one in /usr/bin.

Question: Wrong error message MULTIDRIVEN

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Author Name: Yariv Saliternik
Original Redmine Message: 55 from https://www.veripool.org

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Hi,
I'm trying to compile my design with the verilator and I receive the warning MULTIDRIVEN.
I have checked the verilog code were the message points to and it turned out that as I am using a single very long (1024 bits) to define all my registers (It is done automatically) the verilator sees every always on that vector (although for different bits) as a MULTIDRIVEN vector.
I have checked your documentation and turned off the MULTIDRIVEN warning and the block finished compilation, but now I see that one of the outputs of the block which is 1024 bits long and is driven by the same vector I described above has vanished.

What to do?
Please advise.

Thank you,
Yariv.

$fscanf() and $sscanf()

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Author Name: Holger Wächtler
Original Redmine Issue: 15 from https://www.veripool.org
Original Date: 2008-06-26
Original Assignee: Wilson Snyder (@wsnyder)

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In order to implement testcases, it would be nice to have $fscanf(), $fgets() and $sscanf(). Icarus Verilog implements them in vpi/sys_scanf.c and vpi/sys_fileio.c, maybe some code can get shared if the licenses are compatible.
best Regards,

Question: How to write a test

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Author Name: Wilson Snyder (@wsnyder)
Original Redmine Message: 28 from https://www.veripool.org

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Lane Brooks asked how to write a test.

The BUGS section of bin/verilator has instructions. Please feel free to send edits or edit that yourself with additional notes.

The basic idea is the Verilog is generally self-testing. On fail it prints a message and calls $stop. On pass it calls

         $write("*-* All Finished *-*\n");
         $finish;

You can run a test on Cadence NC Verilog (ncv) or Synopsys VCS by running

cd test_regress
t/t_TESTNAME.pl --nc
t/t_TESTNAME.pl --vcs

You may need minor edits to get this working depending on how you have their programs installed. If you have the GIT checkout, the nodist/invoke_ wrappers are used to solve some of these issues. (If it's the tar'ed kit, these wrappers are skipped and its assumed the NCV files are in your PATH.)

You can run all tests with

  make test

in the top directory. If it's getting too slow it understands how to use multicore; ask for instructions as some additional Perl modules are needed.

The instructions assume the default .cpp top level file; if you need a custom file search for other tests with a .cpp in test_regress/t for example t_func_rand.cpp. Then if you look at t_func_rand.pl you can see the magic for a test with a custom top:

compile (
make_top_shell => 0,
make_main => 0,
v_flags2 => ["--exe t/$Last_Self->{name}.cpp"],
) if $Last_Self->{v3};

Inout signals within modules don't propogate correctly.

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Author Name: Dennis Muhlestein
Original Redmine Issue: 56 from https://www.veripool.org
Original Date: 2009-01-23
Original Assignee: Wilson Snyder (@wsnyder)

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Suppose you have a child module with an input and output signal. The parent only has an inout signal, and uses logic to decide when to drive the signal. If this signal is passed to the child module's input directly, the child module doesn't receive the correct input. If instead, you assign the inout to a separate wire and pass that instead, it works.

Attached patch which adds new test case and exposes the issue as well as shows the workaround.

big bit-endian vs little bit-endian

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Author Name: Rafael Shirakawa
Original Redmine Issue: 36 from https://www.veripool.org
Original Date: 2008-10-15

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Hello,

is there any forecast to verilator accept little bit-endian?

regards,
Rafael

Public function output compile error "non-lvalue statement"

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Author Name: cy wang
Original Redmine Issue: 25 from https://www.veripool.org
Original Date: 2008-07-22
Original Assignee: Wilson Snyder (@wsnyder)

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The attached file is the original verilog code.
verilator --cc my_tt.v
cd obj_dir
make -f Vmy_tt.mk 

the error from gcc
non-lvalue statement.
I trace the generated code.
I guess the left express and right express should be exchanged.

verilator should read files in -f inpfiles in the specified order

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Author Name: Stefan Thiede
Original Redmine Issue: 4 from https://www.veripool.org
Original Date: 2008-04-24
Original Assignee: Wilson Snyder (@wsnyder)

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Even though it's bad practice there are lot's of designs which depend on the order in which files are read (command line and -f inpfiles) due to the fact that they don't cleanly include files with defines.

Verilator is using a set for the verilog files to be read, it would be nice to change that to an ordered list.

V3Options.h:typedef set<string> V3StringSet;
V3Options.h:    V3StringSet     m_vFiles;       // argument: Verilog files to read

Use of // verilator public with inout causes error

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Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 58 from https://www.veripool.org
Original Date: 2009-01-25
Original Assignee: Lane Brooks

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I have a model (of the OpenRISC 1000 SoC) which compiles with Verilator 3.700, albeit with a bucketload of warnings.

I've tried extending it to allow external access to a variable by using a @verilator public@ function:

    // Function to access wb_freeze
    function get_wb_freeze;
       // verilator public
       get_wb_freeze = wb_freeze;
    endfunction // get_wb_freeze

This is in a Verilog file a few levels down the hierarchy. @wb_freeze@ is an input to the module. However when I now build the model, I get a completely unrelated error in the top module:

verilator -Wno-lint -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-UNOPTFLAT -trace -f v_processed.scr \
                 -language 1364-2001 -sc
%Error: rtl/verilog/orpsoc.v:139: Internal Error: ../V3Inst.cpp:94: Width mismatch, should have been handled in pinReconnectSimple
%Error: Command Failed /home/jeremy/tools/verilator/verilator-3.700/verilator_bin -Wno-lint -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-UNOPTFLAT -trace -f v_processed.scr -language 1364-2001 -sc
make: *** [obj_dir/Vorpsoc.mk] Error 10

The problem seems to be use of @// verilator public@. If I remove this the problem goes away (but then I can't access the function, which was the whole point).

I've attached the script file I used for the build (v_processed.scr), the file with the modified function (or1200_ctrl.v) and the top level file (orpsoc.v).

I realize this may be a consequence of the ignored warnings, but I've flagged the issue early in case it is already known. In the meantime I'll address the warnings and try to reproduce the problems in a clean build.

Running under Fedora 9, with GCC 4.3.0 and SystemC 2.2.

$stime()

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Author Name: Holger Wächtler
Original Redmine Issue: 19 from https://www.veripool.org
Original Date: 2008-07-05
Original Assignee: Wilson Snyder (@wsnyder)

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report simulation time as 32bit integer

Question: TriState Implementation

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Author Name: Dennis Muhlestein
Original Redmine Message: 66 from https://www.veripool.org

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Suppose I have two modules which have inout data for a wire.

Verilator will compile the following:

wire data;

module1 m1 ( data );
module2 m2 ( data );

but not the following:

wire d1, d2;
assign d1=d2;
module m1 (d1);
module m2 (d2);

In the latter case, I get an unsupported high-Z construct error. This was part of the problem I was trying to fix yesterday when I wanted to raise the debug level by the way. The error does not print the name of the inputs that are having the problem, the file, or the line number.

In general would you prefer discussion of issues like this 1st or simply filing an issue?

wrong circular logic detect

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Author Name: cy wang
Original Redmine Issue: 26 from https://www.veripool.org
Original Date: 2008-07-23

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The circular logic detector needs to consider index of wire.
The attached file is a simple example to demo it.
Although the design is not circular, verilator detect it as circular design.
Thank you.

Question: Support for tri-state

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Author Name: Lane Brooks
Original Redmine Message: 16 from https://www.veripool.org

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I have been evaluating verilator and find the approach exactly what I want. My only issue with it is the lack of tri-state support. I see that in the TODO file it is a long-term feature. Can you provide me a status update on tristate support? Has there been any work on it yet? Is it a natural extension or does it require a lot of re-architecting?

make $dumpfile(), $dumpvars() no-op when --trace is disabled

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Author Name: Holger Wächtler
Original Redmine Issue: 18 from https://www.veripool.org
Original Date: 2008-07-05

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or, alternatively, use occurences of $dumpfile(), $dumpvars() to let verilator decide whether to generate the trace code or not? Right now the user has to touch two switches (the command line and the source) to enable tracing.

Tristates break when a child modules does has no driver

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Author Name: Lane Brooks
Original Redmine Issue: 54 from https://www.veripool.org
Original Date: 2009-01-22
Original Assignee: Wilson Snyder (@wsnyder)

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This is my issue to fix.

Example that breaks current tristate:

module parent();
childA(.Y(Y));
childB(.Y(Y));
endmodule

module childA(inout Y);
assign Y = (en) ? 1'b0 : 1'bz;
endmodule

module childB(inout Y);
// don't drive Y
endmodule

signal not generated in state machine

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Author Name: Rodney Sinclair
Original Redmine Issue: 46 from https://www.veripool.org
Original Date: 2008-12-27
Original Assignee: Wilson Snyder (@wsnyder)

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The attached code demonstrates a problem with state machines using Verilator 3.681.



After the strobe "myevent", the signal "myevent_pending" should go high for at least one clock cycle, after which STATE_ONE should be entered. The code in tb1.v should have this behavior but it does not -- STATE_ONE is entered immediately after the strobe "myevent". The work around in tb2.v does not have this problem.



To demonstrate:

make -f tb1.mk

obj_dir/Vtb

-- examine "myevent_pending"

make -f tb2.mk

obj_dir/Vtb

-- examine "myevent_pending"

Problem with $fopen translation

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Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 53 from https://www.veripool.org
Original Date: 2009-01-22
Original Assignee: Wilson Snyder (@wsnyder)

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A couple of problems with @$fopen@ (taken from the OpenRISC 1000). I have the original Verilog:

integer fflash;
    initial fflash = $fopen("flash.log");

First problem is that Verilator only accepts the two argument version of @$fopen@ (which returns a file descriptor), rather than the single argument version, which returns a multi-channel descriptor. I tried patching this to

integer fflash;
    initial fflash = $fopen("flash.log","w");

Verilator now works fine, but I get defective C++. The code generated includes:

void Vorpsoc::_initial__TOP(Vorpsoc__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(cout<<"    Vorpsoc::_initial__TOP"<<endl; );
     Vorpsoc* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
     VL_SIGW(__Vtemp1,71,0,3);
     // Body
     // INITIAL at rtl/verilog/mem_if/flash_top.v:330
     __Vtemp1[0] = 0x2e6c6f67;
     __Vtemp1[1] = 0x6c617368;
     __Vtemp1[2] = 0x66;
     VL_EXTENDS_QI(64,32, vlTOPp->v__DOT__flash_top__DOT__fflash) = VL_FOPEN_WI(3, __Vtemp1, 0x77);

This last line prompts the G++ error:

Vorpsoc.cpp:5399: error: lvalue required as left operand of assignment

As far as I can see @VL_EXTENDS_QI@ is an inline function, so should not appear on the LHS of an assignment.

It's not a killer (this is not an important part of the code), but any suggestions on a workaround welcome.

Original Verilog file attached

Thanks, Jeremy

list of file-i/o system tasks, now only partially implemented

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Author Name: Holger Wächtler
Original Redmine Issue: 16 from https://www.veripool.org
Original Date: 2008-06-26
Original Assignee: Wilson Snyder (@wsnyder)

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Hi,
here the list of file-i/o system tasks, some of them are missing to fulfil the 2001 spec. Most of them map directly to libc function calls.

$fopenr
$fopenw
$fopena
$fflush
$fputc
$fgetc
$fgets
$ungetc
$ftell
$fseek
$rewind

Selecting Beyond Signal Bounds Is Possible

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Author Name: Lane Brooks
Original Redmine Issue: 43 from https://www.veripool.org
Original Date: 2008-11-12
Original Assignee: Wilson Snyder (@wsnyder)

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I discovered in verilator that it is possible to select into a wire out side of its boundaries and the selection wraps. e.g.:

wire [1:0] in;
wire [1:0] out32 = in[3:2];
wire [1:0] out10 = in[1:0];

out10 and out32 come out equal. I am not sure what the verilog standard says, but I think I am used to this giving an error in other tools. I have attached a test that shows the behavior.

no STMTDLY warning for always #1 -- blocks

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Author Name: Holger Wächtler
Original Redmine Issue: 22 from https://www.veripool.org
Original Date: 2008-07-14
Original Assignee: Wilson Snyder (@wsnyder)

---

The STMTDLY warning is not necessairy for 'always # 1'-blocks:

/* verilator lint_off STMTDLY */
always # 1 begin
         clk = ~clk;
end

in both cases the inner block should get evaluated every simulation time step, Verilator does essentially the same as other simulators in this case.

So, could the warning for this construct get disabled? (as soon $fopen & Co. are working, this is the last show-stopper for portable testcases. Other simulators run into infinite loops when using 'always begin ... end' without '#1', which works fine in verilator).

Question: Simulating Xilinx Projects

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Author Name: Rodney Sinclair
Original Redmine Message: 9 from https://www.veripool.org

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This is a summary of what I've learned to do to simulate Xilinx projects using Verilator. Using the techniques described here I've been able to shorten simulation times from hours to minutes, although it can take a while (sometimes a few hours) to get the Xilinx unisims models into a form usable with Verilator.

First, the attached archive has everything required to exercise the MULT18X18S model including incorporating the GSR signal in glbl.

1. Extract the files from this archive
2. Copy the MULT18X18S.v file from the verilog/src/unisims directory in your distribution of ISE and then make the following modifications:
   (a) Add "// verilator tracing_off" as the line immediately following the "module" statement (this reduced the amount of garbage you'll get in your waveform files from Xilinx' models);
   (b) Delete the "tri0 GSR" line;
   (c) Change to two occurances of "GSR" to "glbl.GSR";
   (d) Change the "p_out = 36'b0;" statement to "p_out <= 36'b0;"; and
   (e) Get rid of the "#100" delay in the subsequent assignment to "p_out".
   Note: If you don't make changes (b) through (e) you'll get warnings and/or errors from verilator. Try it and you'll see what happens when you try incorporating more of the Xilinx models required by real projects.
3. Type "make -f tb.mk"

Additional comments:

1. The test bench in tb.v isn't a real project. It just requires one of Xilinx' unisims models so that glbl is required and the model has to be converted to a form usable by verilator. It also demonstrates a technique to generate stimuli to the model without requiring problematic "@ (posedge clk)" or "#xxx" delay statements inside an "initial" statement.
2. I haven't been able to successfully convert the Block RAM models provided with ISE. I gave up and put behavioral models in the code. In general, I avoid building Xilinx projects with behavioral models for large memories because I've seen 2 hour build times for projects that had taken 5 minutes total time because ISE required that much additional time to synthesize the large memory into discrete Block RAMs. I've also encountered cases where ISE did not infer a DSP48 primitive when one could be used, and have had to explicitely instantiate the DSP48 so as to get a faster clock.
3. I've been able to simulate the PicoBlaze processor using the provided Verilog source, although it took a couple of hours to resolve all the warnings and errors issued by Verilator about the original source code.

Verilator Doesn't catch duplicate declaration of signal

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Author Name: Rodney Sinclair
Original Redmine Issue: 14 from https://www.veripool.org
Original Date: 2008-06-19

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The attached Verilog file declares the signal "clk" twice, once as an input and once in the body, but no error message is displayed.

A more complicated module with this bad design resulted in error messages that didn't make sense (modules not being recognized or required).

Clock gating support?

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Author Name: Andreas Olofsson
Original Redmine Issue: 50 from https://www.veripool.org
Original Date: 2009-01-20

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What is the status of clock gating support? The documentation mentions putting clock_enable on clock enable signals, but it says the feature is experimental.I am getting failures with clock gating and I am pretty sure it's glitch related.

Here is my clock gating construct.

always @ (/AS/clk or en)
if(~clk)
en_sh <=en;

assign qclk = clk & en_sh

In some simulators there would usually be a way to debug these phantom glitches by "expanding an event". What would be the best way to debug this problem in verilator generated code. It might be a good thing to add to the FAQ.

Andreas

Missing header in V3Ast.cpp

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Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 40 from https://www.veripool.org
Original Date: 2008-10-25
Original Assignee: Wilson Snyder (@wsnyder)

---

Using GCC 4.3 on Fedora 9 and Verilator 3.680.

I found I had to add the following C header to V3Ast.cpp

#include <string.h>

This is because the code uses the C function strncmp.

Thereafter the code compiled, but make test failed with:

g++ -I. -MMD -I/home/jeremy/tools/verilator/verilator-3.680/test_c/../include -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0 -DVL_DEBUG=1 -c -o Vtop__ALLcls.o Vtop__ALLcls.cpp
g++: linux: No such file or directory
g++: linux: No such file or directory
make[2]: *** [sim_main.o] Error 1
make[2]: *** Waiting for unfinished jobs....
make[2]: *** [verilated.o] Error 1
make[2]: Leaving directory /home/jeremy/tools/verilator/verilator-3.680/test_c/obj_dir' make[1]: *** [compile] Error 2 make[1]: Leaving directory /home/jeremy/tools/verilator/verilator-3.680/test_c'
make: *** [test_c] Error 2

However verilator seems to run OK.

HTH,

Jeremy

gate_instantiation .. name_of_gate_instance should allow range (1364-2001)

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Author Name: Stefan Thiede
Original Redmine Issue: 3 from https://www.veripool.org
Original Date: 2008-04-24
Original Assignee: Wilson Snyder (@wsnyder)

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Verilator 3.661 2008/04/04 rev1022

verilator test.v --lint-only
%Error: test.v:7: syntax error, unexpected '[', expecting '('
%Error: Cannot continue

module test(a, b);
     parameter
         Bits = 32;
     input  [Bits-1:0] a;
     output [Bits-1:0] b;

     buf bufdint [Bits-1:0] (b, a);
endmodule

Question: Cross compiling on linux and windows

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Author Name: jp mack
Original Redmine Message: 31 from https://www.veripool.org

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Hi Wilson,

Greetings! I am new here in verilator and it is indeed a great tool in my opinion. I have used it on RHL and it works splendid.
However, how do you run cross compiling on linux and windows? We would like to compile and run the verilated files from linux to windows platform

Thanks in advance!

Missing header in Verilator 3.700

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Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 52 from https://www.veripool.org
Original Date: 2009-01-22
Original Assignee: Wilson Snyder (@wsnyder)

---

Compiling with GCC 4.3.0 under Fedora 9:

Missing header (for @sort()@ function) in @V3Const.cpp@. Adding

#include <algorithm>

fixes this.

System details from uname -a

Linux thomas 2.6.27.9-73.fc9.i686 #1 SMP Tue Dec 16 15:25:05 EST 2008 i686 i686 i386 GNU/Linux

GCC version details (Fedora 9 standard):

Using built-in specs.
Target: i386-redhat-linux
Configured with: ../configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --with-bugurl=http://bugzilla.redhat.com/bugzilla --enable-bootstrap --enable-shared --enable-threads=posix --enable-checking=release --with-system-zlib --enable-__cxa_atexit --disable-libunwind-exceptions --enable-languages=c,c++,objc,obj-c++,java,fortran,ada --enable-java-awt=gtk --disable-dssi --enable-plugin --with-java-home=/usr/lib/jvm/java-1.5.0-gcj-1.5.0.0/jre --enable-libgcj-multifile --enable-java-maintainer-mode --with-ecj-jar=/usr/share/java/eclipse-ecj.jar --disable-libjava-multilib --with-cpu=generic --build=i386-redhat-linux
Thread model: posix
gcc version 4.3.0 20080428 (Red Hat 4.3.0-8) (GCC) 

git build fails due to missing config_rev.h

---

Author Name: Holger Wächtler
Original Redmine Issue: 17 from https://www.veripool.org
Original Date: 2008-07-04
Original Assignee: Wilson Snyder (@wsnyder)

---

Hi,
since config_rev.h is generated from the SVN versioning number by config_rev.pl, this approach fails when using the git tree: the .svn directories are missing. I'm not sure about the correct fix, should a special git tag or number be used?
best regards,

Warning UNOPTFLAT written to stdout, not stderr

---

Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 59 from https://www.veripool.org
Original Date: 2009-01-26
Original Assignee: Wilson Snyder (@wsnyder)

---

Most warnings are written to the standard error stream, so I can capture all the warnings in a file with a command like:

make -f linux.mk clean verilate 2>/tmp/log

However UNOPTFLAT messages are written to stdout, so will not appear in this log file. This appears to be inconsistent.

sensitivity list

---

Author Name: Rafael Shirakawa
Original Redmine Issue: 37 from https://www.veripool.org
Original Date: 2008-10-17

---

Hi,

Can verilator support sensitivity list with edges and activity wires?

like this example will generate an error:

module example;

wire a;
wire b;
wire c;


always @(a or negedge b) 
begin
  if ( b == 1'b0)
  begin
     c = a;
  end
end

endmodule

and this other one will translate without any error:

module example;

wire a;
wire b;
wire c;


always @(a) 
begin
  if ( b == 1'b0)
  begin
     c = a;
  end
end

always @(negedge b) 
begin
  if ( b == 1'b0)
  begin
     c = a;
  end
end

endmodule

Question: Calling a function

---

Author Name: Aki Niimura
Original Redmine Message: 23 from https://www.veripool.org

---

Hello everyone,

I'm very new to verilator and no longer familiar with C++.

I finally managed to install verilator and managed to compile a synthesizable RTL code to C++.
I'm using --cc option to produce C++ code.

Now, I would like to call an outside C fumction from one module.
It was suggested in the documentation that I should use $c("...") to embed a C++ code, which I did.

The problem I'm having is where to put my extra functions.
I think there are two possible places:
(1) Adding private methods under VLMODULE class, where all verilog functionalities are implemented.
Problem - those codes (Vtop.cpp and Vtop.h, for example) are automatically generated so that the changes I made are gone once I rerun 'verilator'.
(2) Creating functions outside and call them as global functions
Problem - Compiling Vtop.cpp complains that it doesn't know anything about such functions
Adding #include "myfunc.h" would solve such problem but the changes will be gone when I rerun 'verilator'.

I tried to find good examples that use $c() but so far I couldn't find any good examples.

Could anybody recommend me a right way to call outside functions?

If somebody has some working verilator projects that are available to public, I love to know such examples.
(What I found was one DFF example, which is too small ...)

Thank you for your attention and sorry for this newbie question.

Best regards,
Aki Niimura

synopsys translate_off and synopsys translate_on

---

Author Name: cy wang
Original Redmine Issue: 24 from https://www.veripool.org

---

//synopsys translate_off
      non-synthesizable code
//synopsys translate on

I comment this region by hand.
If verilator can automatically do it, It will reduce manual effort.

clocks and signals not recognized in generate loops

---

Author Name: Rodney Sinclair
Original Redmine Issue: 45 from https://www.veripool.org
Original Date: 2008-11-22
Original Assignee: Wilson Snyder (@wsnyder)

---

The attached source illustrates two error messages associated with clocks and registers within generate statements:



verilator --cc tb1.v tb.cc # bussed clocks

verilator --cc tb2.v tb.cc # bussed output (work around for bussed clocks)

verilator --cc tb3.v tb.cc # work around for both busses

GCC 4.3 header file cleanup problem

---

Author Name: Lane Brooks
Original Redmine Issue: 47 from https://www.veripool.org
Original Date: 2009-01-09
Original Assignee: Wilson Snyder (@wsnyder)

---

GCC 4.3 requires you to add
#include
to the V3Const.cpp to find the sort() definition.

Tristate: Tracing an inout signal is broken

---

Author Name: Lane Brooks
Original Redmine Issue: 55 from https://www.veripool.org
Original Date: 2009-01-22
Original Assignee: Wilson Snyder (@wsnyder)

---

Conventionally when you trace a tristate signal the driven signal propagates up and down the hierarchy to all modules because the buses are supposed to be physically connected. This does not happen in the current implementation.

In the current implementation, the inout signal is converted to an output with the same name and an input signal with __in appended to it. So when a module drives the bus, its own signal correctly propagates up the hierarchy through the output port, but it does not properly propagate down to the children through their output ports (as expected). It does, however, propagate down the __in signal (also as expected). Wilson had talked about doing some stuff during the vcd generation to create 'Z and `X correctly, and perhaps this is the correct place to deal with this issue as well, but I think if I just switch the role and turn the original signal into the input and create an __out signal instead, then the traced signal will be more like conventional usage. This does not solve the 'Z and 'X issue, but makes the experience more traditional. The __out signal can then be dropped from the vcd dump as it contains no useful information for the trace.

can't convert a FUNCREF to constant

---

Author Name: Stefan Thiede
Original Redmine Issue: 6 from https://www.veripool.org
Original Date: 2008-05-01

---

Verilator 3.662 2008/04/25 rev1042

verilator test.v --lint-only

%Warning-WIDTH: test.v:13: Operator FUNCREF expects 32 bits on the Function Argument, but Function Argument's VARREF generates 15 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: test.v:13: Expecting expression to be constant, but can't convert a FUNCREF to constant.
%Error: test.v:15: Expecting expression to be constant, but variable isn't const: SIZE
%Error: test.v:15: Can't convert defparam value to constant: Param __paramNumber1 of a
%Error: Exiting due to 4 warning(s)
%Error: Command Failed verilator_bin test.v --lint-only


module test();

  parameter WORDS = 15'h700;
  
  function integer dumdi (input integer x);
     begin
       x = x - 1;
       for (dumdi=0; x>0; dumdi=dumdi+1)
         x = x >> 1;
     end
  endfunction

  localparam SIZE = dumdi(WORDS);

  b #(SIZE) a();

endmodule

module b();

  parameter SIZE = 15;

endmodule

Comiplation with gcc 4.3 fails due to header file cleanup

---

Author Name: Lane Brooks
Original Redmine Issue: 35 from https://www.veripool.org
Original Date: 2008-10-15
Original Assignee: Wilson Snyder (@wsnyder)

---

I found the latest git version of verilator does not compile with gcc 4.3.
It produces a strncmp not found error. As explained at http://gcc.gnu.org/gcc-4.3/porting_to.html, gcc-4.3 cleans up the header files. The solution is simply to #include to V3Ast.cpp

Question: Raising the debug level.

---

Author Name: Dennis Muhlestein
Original Redmine Message: 62 from https://www.veripool.org

---

Browsing around in the verilator source, I see UINFO usage with different debug levels. I can't seem to find the command line option for enabling the higher level though.

--debug is showing the UINFO(2.... but not UNFO(9... for instance.

incomplete IO port list

---

Author Name: Guy-Armand Kamendje
Original Redmine Issue: 32 from https://www.veripool.org
Original Date: 2008-09-20
Original Assignee: Wilson Snyder (@wsnyder)

---

I also noticed that Verilator 3.665 will accept modules with incomplete IO port list. I am not very familiar with the Verilog standard but I noticed that synthesis tool will rather flag a severe error in such cases. What I mean is the following:

module foo(clk, reset );
input clk; // <== clock signal
input reset; // <== reset signal
input work_in; // <==
endmodule

Omitting to include the signal work_in in the port list does not result in a error. Is there a compiler option that has to be set in order to catch these cases?

documentation issue /*verilator public*/

---

Author Name: Holger Wächtler
Original Redmine Issue: 27 from https://www.veripool.org
Original Date: 2008-07-30
Original Assignee: Wilson Snyder (@wsnyder)

---

Hi,
is the explanation of the documentation (website) correctly describing the access of private module signals?
shouldn't "top->v.signal" read "top->v->signal"?

/*verilator public*/

---

Author Name: Rafael Shirakawa
Original Redmine Issue: 41 from https://www.veripool.org
Original Date: 2008-10-27
Original Assignee: Wilson Snyder (@wsnyder)

---

Hello,

after I translate this code:

module example(
     input clk,
     input a);

reg b/*verilator public*/;

always @(posedge clk) begin
     b <= a;
end

endmodule

the translated code wouldn't accept my main file to force the value of one variable:

#include <verilated.h>
#include "Vexample.h"

Vexample *top;
unsigned int main_time = 0;

double sc_time_stamp () {
     return main_time;
}

main() {
int clk;
top = new Vexample;
top->a = 0;
top->clk = 0;
int not_finished (1);

while (not_finished) {

     if (main_time % 5 == 0) {
         if (clk == 0) {clk = 1;}
         else          {clk = 0;}
     }
     top->clk = clk;

     if (main_time >= 15 && main_time <= 35 ) {top->a = 1;}
     else {top->a = 0;}
     if (main_time >= 45 && main_time <= 55 )
         {top->v->b = 1;} // this will return an error

     if (main_time == 100) {not_finished = 0;}

     main_time ++;
     top->eval();
}

top->final();

}

I took this line command to make the translation:

verilator -cc example.v -exe main_example.cpp

I'm pretty sure that I am doing something wrong, but this is the way the manual describes /verilator public/ usage. I have also tried @top->b@ with no success...

where is my mistake..?

thanks,
Rafael

invalid types `SData[int]' for array subscript

---

Author Name: Ralf Karge
Original Redmine Issue: 44 from https://www.veripool.org
Original Date: 2008-11-19
Original Assignee: Wilson Snyder (@wsnyder)

---

I received new RTL code that causes Verilator to generate illegal C-code. Attached a small test case triggering the same problem.

$ perl $VERILATOR_ROOT/bin/verilator --cc -x-assign 0 --stats -Wno-WIDTH tb_ip_shell.v

$ cd obj_dir

$ make -f Vtb_ip_shell.mk

g++ -I. -MMD -I/cygdrive/c/Projects/Verilator-3.681/include -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0 -c -o Vtb_ip_shell__ALLcls.o Vtb_ip_shell__ALLcls.cpp
In file included from Vtb_ip_shell__ALLcls.cpp:1:
Vtb_ip_shell.cpp: In static member function static void Vtb_ip_shell::_sequent__TOP__1(Vtb_ip_shell__Syms*)': Vtb_ip_shell.cpp:127: error: invalid types SData[int]' for array subscript
Vtb_ip_shell.cpp:128: error: invalid types SData[int]' for array subscript Vtb_ip_shell.cpp:129: error: invalid types SData[int]' for array subscript
Vtb_ip_shell.cpp:130: error: invalid types `SData[int]' for array subscript
make: *** [Vtb_ip_shell__ALLcls.o] Error 1

Question: UNOPTFLAT

---

Author Name: Radu Hobincu
Original Redmine Message: 3 from https://www.veripool.org

---

Hello,

I have a problem simulating this structure:

wire [dataWidth_bcm-1:0] inMask [0:numberOfInputs-1];
wire [dataWidth_bcm-1:0] inMaskLink [0:numberOfInputs-1];
wire [numberOfInputs_log-1:0] seqSelectedIn_out_mask [0:numberOfInputs-1];
wire [numberOfInputs_log-1:0] seqSelectedIn_out_maskLink [0:numberOfInputs-1];

generate for( i = 0; i < numberOfInputs; i = i + 1 ) begin: inputMask
         assign inMask[i] = {seqPriority_in[(i+1)*priorityWidth-1:i*priorityWidth],
                             seqData_in[(i+1)*dataWidth-1:i*dataWidth]} &
                                 {(dataWidth_bcm){dataSelect[i]}};
         assign seqSelectedIn_out_mask[i] = dataSelect[i] ? i : 0; 
end
endgenerate

assign inMaskLink[0] = inMask[0];
assign seqSelectedIn_out_maskLink[0] = seqSelectedIn_out_mask[0];
generate for( i = 1; i < numberOfInputs; i = i + 1 ) begin: inputMaskInterLink
         assign  inMaskLink[i] = inMask[i]|inMaskLink[i-1];
         assign  seqSelectedIn_out_maskLink[i] = seqSelectedIn_out_mask[i]|seqSelectedIn_out_maskLink[i-1];
end
endgenerate

Firstly, it throws an UNOPTFLAT warning for signal inMaskLink:

%Warning-UNOPTFLAT: Arbiter_v3.v:184: Signal unoptimizable: Feedback to clock or circular logic: TOP->v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink
%Warning-UNOPTFLAT:      Example path: Arbiter_v3.v:184:  TOP->v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink
%Warning-UNOPTFLAT:      Example path: Arbiter_v3.v:199:  ASSIGNW
%Warning-UNOPTFLAT:      Example path: Arbiter_v3.v:184:  TOP->v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink

Then, it throws an error:

%Error: Arbiter_v3.v:184: Unsupported: Can't detect changes on arrayed variable (probably with UNOPTFLAT warning suppressed): v.ubc_top.inStorageInterface.arbiter4_v3.gen_arbiter.inMaskLink

Verilator probably believes that the second generate is a circular CLC assignment but actually it's not. Any suggestions please?

prefix problem

---

Author Name: cy wang
Original Redmine Issue: 23 from https://www.veripool.org
Original Date: 2008-07-20

---

./configure --prefix=/XX/local;make;make install
the following files are installed.
-->
/XX/local/bin/verilator
/XX/local/bin/verilator_bin
/XX/local/share/verilator/include
/XX/local/share/verilator/src

setenv VERILATOR_ROOT /XX/local/share/verilator
or
setenv VERILATOR_ROOT /XX/local

verilator -cc xx.v

all have problems

parameters

---

Author Name: Rafael Shirakawa
Original Redmine Issue: 38 from https://www.veripool.org
Original Date: 2008-10-21
Original Assignee: Wilson Snyder (@wsnyder)

---

Hi,

Verilator is not able to unroll generators loops like this:

module example;

wire clk;
wire a [9:0];
reg [1:0] b [9:0];
integer j;

generate
     genvar i;
     for (i=0; i<2; i=i+1) begin
         always @(posedge clk) begin
             for (j=0; j<10; j=j+1) begin
                 if (a[j])
                     b[i][j] <= 1'b0;
                 else
                     b[i][j] <= 1'b1;
             end
         end
     end
endgenerate

endmodule

Mixing tristate and low-Z drivers. Error Msg unclear.

---

Author Name: Dennis Muhlestein
Original Redmine Issue: 51 from https://www.veripool.org
Original Date: 2009-01-21
Original Assignee: Wilson Snyder (@wsnyder)

---

When you get this Error message, there is no additional information that tells you the name of the signal, the file, or line number that is causing verilator to throw the Error.

Workaround 1: use @--debugi=9@
This causes an inordinate amount of output on a big model.

Workaround 2: recompile verilator with higher debug level in V3Tristate.cpp

Compilation problem on Windows for Visual Studio 2005

---

Author Name: John Stroebel
Original Redmine Issue: 42 from https://www.veripool.org
Original Date: 2008-10-27
Original Assignee: Wilson Snyder (@wsnyder)

---

I am currently using version 3.670 of Verilator.
I receive a few errors when compiling verilated code in Visual Studio 2005 on Windows. In verilated.cpp I needed to add "#include " to remove a bunch of compile-time errors. I still get an error in function VL_FGETS_IXQ because of the following line of code:
char buffer[bytes];
The compiler is expecting a constant expression for the size of buffer. "bytes" is a variable.
Finally, in verilatedos.h, I had to modify the typedef of uint32_t in the _WIN32 section from:
typedef unsigned long uint32_t; ///< 32-bit unsigned type (backward compatibility)
to
typedef unsigned int uint32_t; ///< 32-bit unsigned type (backward compatibility)