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View Code? Open in Web Editor NEWsynthesizable FFT IP block for FPGA designs
License: Other
synthesizable FFT IP block for FPGA designs
License: Other
Hi, I'm a master degree engegneering student. I've a project in wich I have to implement a 16-bit hardware SPI FFT and IFFT with 128 samples window at time. I'm simulating your code using Quartus II and Altera ModelSim.
In your testbench I can see only an FFT transformation but not an IFFT. Did you implemented it yet? if yes, how do I select wich algorithms to use?
I see in you code these four signals:
d_re
d_im
q_re
q_im
I think that this implementation would do also the IFFT otherwise I can't understand the d_im existance.
I also want to ask you if these warings I obtain simulating your code are normal:
# ** Warning: NUMERIC_STD.TO_UNSIGNED: vector truncated
# Time: 99500 ns Iteration: 0 Instance: /fft_tb/dut/all_instances(6)/first_stages_only/tf_rom
# ** Warning: NUMERIC_STD.TO_UNSIGNED: vector truncated
# Time: 99700 ns Iteration: 0 Instance: /fft_tb/dut/all_instances(6)/first_stages_only/tf_rom
# ** Warning: NUMERIC_STD.TO_UNSIGNED: vector truncated
# Time: 99900 ns Iteration: 0 Instance: /fft_tb/dut/all_instances(6)/first_stages_only/tf_rom
Simulation duration lasts 80.000ns for me. Is it also normal?
Thank you for your attention :)
Hi,
I tried to run the test bench by typing make in fft/vrf folder. I got following error.
(base) D:\Work\Vivado\Booster_BbyB\fft-thasti\fft\vrf>make
make results.xml
make[1]: Entering directory '/d/Work/Vivado/Booster_BbyB/fft-thasti/fft/vrf'
make[1]: *** No rule to make target '/../../counter/rtl/counter.vhd', needed by
'analyse'. Stop.
make[1]: Leaving directory '/d/Work/Vivado/Booster_BbyB/fft-thasti/fft/vrf'
C:\Users\DELL\Anaconda3\Lib\site-packages\cocotb\share/makefiles/Makefile
.sim:79: recipe for target 'sim' failed
make: *** [sim] Error 2
Kindly suggest a solution for this.
Thank you.
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